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74AC10

  

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Match, Like 74AC10 74AC109 74AC10B 74AC10M
Start with 74AC109* 74AC10B* 74AC10C* 74AC10M* 74AC10P* 74AC10S* 74AC10T*
End *V74AC10 *D74AC10 *C74AC10 *N74AC10
Included *74AC107* *74AC109* *74AC10D* *74AC10E* *74AC10F* *74AC10M* *74AC10N* *74AC10P*
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Fairchild
Fairchild Semiconductor
74AC10 Triple 3-Input NAND Gate

General Description
The AC/ACT10 contains three, 3-input NAND gates.

Features
■ ICC reduced by 50% on 74AC only
■ Outputs source/sink 24mA


other parts : 74ACT10  74AC10SC  74AC10SJ  74AC10MTC  74ACT10SC  74ACT10MTC  74AC10SCX  74AC10SJX  74AC10MTCX  74AC10PC  
74AC10 PDF
Fairchild
Fairchild Semiconductor
74AC10_2000 Triple 3-Input NAND Gate

General Description
The AC/ACT10 contains three, 3-input NAND gates.

Features
■ ICC reduced by 50% on 74AC only
■ Outputs source/sink 24 mA


other parts : 74AC10MTC_2000  74AC10MTCX_2000  74AC10PC_2000  74AC10SC_2000  74AC10SCX_2000  74AC10SJ_2000  74AC10SJX_2000  74ACT10PC_2000  74ACT10SC_2000  74ACT10SCX_2000  
74AC10 PDF
ST-Microelectronics
STMicroelectronics
74AC10_1997 TRIPLE 3-INPUT NAND GATE

DESCRIPTION
The AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL =24 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC10B_1997  74AC10M_1997  
74AC10 PDF
Fairchild
Fairchild Semiconductor
74AC10_2005 Triple 3-Input NAND Gate

General Description
The AC/ACT10 contains three, 3-input NAND gates.

Features
■ ICC reduced by 50% on 74AC only
■ Outputs source/sink 24 mA


other parts : 74AC10MTC_2005  74AC10MTCX_2005  74AC10PC_2005  74AC10PC-NL_2005  74AC10PC_NL_2005  74AC10SC_2005  74AC10SCX_2005  74AC10SJ_2005  74AC10SJX_2005  74ACT10PC_2005  
74AC10 PDF
ST-Microelectronics
STMicroelectronics
74AC10 TRIPLE 3-INPUT NAND GATE

DESCRIPTION
The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 2µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC10B  74AC10M  74AC10MTR  74AC10TTR  
74AC10 PDF
ST-Microelectronics
STMicroelectronics
74AC10M_1997 TRIPLE 3-INPUT NAND GATE

DESCRIPTION
The AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL =24 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC10_1997  74AC10B_1997  
74AC10M PDF
ONSEMI
ON Semiconductor
74AC109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs


other parts : 74ACT109  MC74AC109  MC74ACT109  MC74AC109N  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74ACT109N  MC74ACT109D  
74AC109 PDF
ST-Microelectronics
STMicroelectronics
74AC10B TRIPLE 3-INPUT NAND GATE

DESCRIPTION
The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 2µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC10  74AC10M  74AC10MTR  74AC10TTR  
74AC10B PDF
ON-Semiconductor
ON Semiconductor
74AC109 Dual JK Positive Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
   Asynchronous Inputs:
      LOW input to SD (Set) sets Q to HIGH level
      LOW input to CD (Clear) sets Q to LOW level
      Clear and Set are independent of clock
      Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs


other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109DR2  MC74AC109DT  MC74AC109DTR2  MC74AC109M  MC74AC109MEL  MC74AC109N  MC74ACT109  
74AC109 PDF
ST-Microelectronics
STMicroelectronics
74AC10M TRIPLE 3-INPUT NAND GATE

DESCRIPTION
The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology.
The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 2µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28 % VCC (MIN.)
■ 50Ω TRANSMISSION LINE DRIVING CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 24mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 10
■ IMPROVED LATCH-UP IMMUNITY


other parts : 74AC10  74AC10B  74AC10MTR  74AC10TTR  
74AC10M PDF
Fairchild
Fairchild Semiconductor
74AC109 Dual JK Positive Edge-Triggered Flip-Flop

General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.

Features
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT109 has TTL-compatible inputs


other parts : 74AC109MTC  74AC109MTCX  74AC109PC  74AC109PCX  74AC109SC  74AC109SCX  74AC109SJ  74AC109SJX  74ACT109  74ACT109CW  
74AC109 PDF
Motorola
Motorola => Freescale
74AC109 Dual JK positive edge-triggered flip-flop

The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA
• ′ACT109 Has TTL Compatible Inputs


other parts : 74ACT109  MC74AC109  MC74AC109D  MC74AC109N  MC74ACT109  MC74ACT109D  MC74ACT109N  
74AC109 PDF

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