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Y2578 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
Y2578 5-V ANALOG, 3-/5-V DIGITAL, 14-/12-BIT, 200-KSPS, 4-/8-CHANNEL SERIAL ANALOG-TO-DIGITAL CONVERTERS WIRH ±10-V INPUTS TI
Texas Instruments TI
Y2578 Datasheet PDF : Y2578 pdf   
TLC3578 image

description
The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host.

● 14-Bit Resolution for TLC3574/78, 12-Bit for
   TLC2574/2578
● Maximum Throughput 200-KSPS
● Multiple Analog Inputs:
   − 8 Single-Ended Channels for
      TLC3578/2578
   − 4 Single-Ended Channels for
      TLC3574/2574
● Analog Input Range: ±10 V
● Pseudodifferential Analog Inputs
● SPI/DSP-Compatible Serial Interfaces With
   SCLK up to 25-MHz
● Built-In Conversion Clock and 8x FIFO
● Single 5-V Analog Supply; 3-/5-V Digital
   Supply
● Low-Power
   − 5.8 mA in Normal Operation
   − 20 µA in Power Down
● Programmable Autochannel Sweep and
   Repeat
● Hardware-Controlled, Programmable
   Sampling Period
● Hardware Default Configuration
● INL:
   TLC3574/78: ±1 LSB;
   TLC2574/78: ±0.5 LSB
● DNL:
   TLC3574/78: ±0.5 LSB;
   TLC2574/78: ±0.5 LSB
● SINAD:
   TLC3574/78: 79 dB;
   TLC2574/78: 72 dB
● THD:
   TLC3574/78: −82 dB;
   TLC2574/78: −82 dB

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