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SN65LVDS116 Datasheet PDF - Texas Instruments

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SN65LVDS116 Datasheet PDF : SN65LVDS116 pdf   
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The SN65LVDS116 is one differential line receiver connected to sixteen differential line drivers that
implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers the low-power, low-noise coupling, and fast switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

• One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements
   of ANSI EIA/TIA-644 Standard
• Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
• Enabling Logic Allows Separate Control of Each Bank of Four Channels
   or 2-Bit Selection of Any One of the Four Banks
• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load
• Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL,
   or HSTL Outputs With External Termination Networks
• Propagation Delay Times < 4.7 ns
• Output Skew Is < 300 ps and Part-to-Part Skew < 1.5 ns
• Total Power Dissipation Typically 470 mW With All Ports Enabled and at 200 MHz
• Driver Outputs or Receiver Input Is High Impedance When Disabled or With VCC < 1.5V
• Bus-Pin ESD Protection Exceeds 12 kV
• Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch

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