The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.
Skew parameters are specified for a reduced temperature and voltage range common to many applications.
The CDC208 is characterized for operation from −40°C to 85°C.
● Low-Skew Propagation Delay
Specifications for Clock-Driver
● TTL-Compatible Inputs and
● Flow-Through Architecture Optimizes
● Center-Pin VCC and GND Pin
Configurations Minimize High-Speed
● EPIC ™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
● 500-mA Typical Latch-Up Immunity at
● Package Options Include Plastic