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74LVT18512DGGRG4 Datasheet PDF - TI

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Part Number74LVT18512DGGRG4 TI
Texas Instruments TI
Description3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
74LVT18512DGGRG4 Datasheet PDF : 74LVT18512DGGRG4 pdf   74LVT18512DGGRG4 pdf   

Image Info : [TI] SN74LVT18512

description
The ’LVT18512 and ’LVT182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

• Members of the Texas Instruments SCOPE™ Family of Testability Products
• Members of the Texas Instruments Widebus™ Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• B-Port Outputs of ’LVT182512 Devices Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required
• Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE™ Instruction Set
   – IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
   – Parallel-Signature Analysis at Inputs
   – Pseudo-Random Pattern Generation From Outputs
   – Sample Inputs/Toggle Outputs
   – Binary Count From Outputs
   – Device Identification
   – Even-Parity Opcodes
• Package Options Include 64-Pin Plastic
   Thin Shrink Small Outline (DGG) and 64-Pin
   Ceramic Dual Flat (HKC) Packages Using
   0.5-mm Center-to-Center Spacings

 

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