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74LV138 Datasheet PDF - Texas Instruments

Part NameDescriptionManufacturer
74LV138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS TI
Texas Instruments TI
74LV138 Datasheet PDF : 74LV138 pdf   
SN74LV138 image

description
These 3-line to 8-line decoders/demultiplexers are designed for 2.7-V to 5.5-V VCC operation. The ’LV138 are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

● EPIC  (Enhanced-Performance Implanted CMOS) 2-µ Process
● Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C
● Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C
● ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
● Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
● Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs

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