These triple 3-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation.
The ’LV10A devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
● 2-V to 5.5-V VCC Operation
● Max tpd of 7 ns at 5 V
● Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
● Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
● Ioff Supports Partial-Power-Down Mode Operation
● Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
● ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)