The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
• In accordance with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTE flow-through pin-out architecture
• Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V.