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NB6L11DTG Datasheet PDF - ON Semiconductor

Part NumberNB6L11DTG ON-Semiconductor
ON Semiconductor ON-Semiconductor
Description2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
NB6L11DTG Datasheet PDF : NB6L11DTG pdf   
NB6L11DR2 image

2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator

  The NB6L11 is an enhanced differential 1:2 clock or data fanout buffer/translator. The device has the same pinout and is functionally equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW jitter and LOW power consumption.
  Differential input can be configured to accept single−ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML, or LVDS. The outputs are 800 mV ECL signals.

Features
•Maximum Input Clock Frequency 6 GHz Typical
•Maximum Input Data Rate 6 Gb/s Typical
•Low 14 mA Typical Power Supply Current
•150 ps Typical Propagation Delay
•5 ps Typical Within Device Skew
•75 ps Typical Rise/Fall Times
•PECL Mode Operating Range:
   VCC= 2.375 V to 3.465 V with VEE = 0 V
•NECL Mode Op rating Range:
   VCC= 0 V with VEE = −2.375 V to −3.465 V
•Open Input Default State
•Q Outputs Will Default LOW with Inputs Open or at VEE
•LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input Compatible
•Pb−Free Packages are Available

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