The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 12 master−slave flip−flops. The output of each flip−flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative−going edge of the Clock input. Reset is asynchronous and active−high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With JEDEC Standard No. 7A Requirements
• Chip Complexity: 398 FETs or 99.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant