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74HC138-Q100 Datasheet PDF - NXP Semiconductors.

Part NameDescriptionManufacturer
74HC138-Q100 3-to-8 line decoder/demultiplexer; inverting NXP
NXP Semiconductors. NXP
74HC138-Q100 Datasheet PDF :   
74HC138-Q100 image

The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). The 74HC138-Q100; 74HCT138-Q100 decoder accepts three binary weighted address inputs (A0, A1 and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0to Y7).

The 74HC138-Q100; 74HCT138-Q100 featuresthree enable inputs: two active LOW(E1 and E2) and one active HIGH(E3). Every output will be HIGH unless E1 and E2are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the 74HC138-Q100; 74HCT138-Q100 to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138-Q100;74HCT138-Q100 ICs and one inverter. The 74HC138-Q100; 74HCT138-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes.

Not used enable inputs must be permanently tied to their appropriate active HIGH- or LOW-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.


* Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 - Specified from 40C to +85C and from 40C to +125C
* Demultiplexing capability
* Multiple input enable for easy expansion
* Complies with JEDEC standard no. 7A
* Ideal for memory chip select decoding
* Active LOW mutually exclusive outputs
* ESD protection:
 - MIL-STD-883, method 3015 exceeds 2000 V
 - HBM JESD22-A114F exceeds 2000 V
 - MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
* Multiple package options


 

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