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74AHC132PW Datasheet PDF - NXP Semiconductors.

Part Number74AHC132PW NXP
NXP Semiconductors. NXP
DescriptionQuad 2-input NAND Schmitt trigger
74AHC132PW Datasheet PDF : 74AHC132PW pdf   
74AHC132 image

General description
The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage VT+ and the negative VT− is defined as the hysteresis voltage VH.

Features
■ Balanced propagation delays
■ Inputs accept voltages higher than VCC
■ Input levels:
   ◆ For 74AHC132: CMOS level
   ◆ For 74AHCT132: TTL level
■ ESD protection:
   ◆ HBM EIA/JESD22-A114E exceeds 2000 V
   ◆ MM EIA/JESD22-A115-A exceeds 200 V
   ◆ CDM EIA/JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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