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74AHC125PW-T Datasheet PDF - NXP Semiconductors.

Part Name
Description
Manufacturer
74AHC125PW-T
NXP
NXP Semiconductors. NXP
Other PDF
  no available.
PDF
74AHC125PW-T Datasheet PDF : 74AHC125PW-T pdf     
74AHC125 image

General description
The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active LOW enable inputs.

Features
■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than VCC
■ For 74AHC125 only: operates with CMOS input levels
■ For 74AHCT125 only: operates with TTL input levels
■ ESD protection:
   ◆ HBM JESD22-A114E exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V
   ◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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