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FW82371AB Datasheet PDF - Intel

Part NumberFW82371AB Intel
Intel Intel
DescriptionPCI-TO-ISA / IDE XCELERATOR (PIIX4)
FW82371AB Datasheet PDF : FW82371AB pdf   
FW82371AB image

The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-ISA bridge
function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management
function. As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC
systems—two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real
Time Clock.

Supported Kits for both Pentium® and Pentium® II Microprocessors
  82430TX ISA Kit
  82440LX ISA/DP Kit
Multifunction PCI to ISA Bridge
  Supports PCI at 30 MHz and 33 MHz
  Supports PCI Rev 2.1 Specification
  Supports Full ISA or Extended I/O (EIO) Bus
  Supports Full Positive Decode or Subtractive Decode of PCI
  Supports ISA and EIO at 1/4 of PCI Frequency
Supports both Mobile and Desktop Deep Green Environments
  3.3V Operation with 5V Tolerant Buffers
  Ultra-low Power for Mobile Environments Support
  Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft OFF System States
  All Registers Readable and Restorable for Proper Resume from 0.V Suspend
Power Management Logic
  Global and Local Device Management
  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers
  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation
Enhanced DMA Controller
  Two 82C37 DMA Controllers
  Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA Protocols (Simultaneously)
  Fast Type-F DMA for Reduced PCI Bus Usage
Interrupt Controller Based on Two 82C59
  15 Interrupt Support
  Independently Programmable for Edge/Level Sensitivity
  Supports Optional I/O APIC
  Serial Interrupt Input
Timers Based on 82C54
  System Timer, Refresh Request, Speaker Tone Output
USB
  Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
  Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse
  Supports UHCI Design Guide
SMBus
  Host Interface Allows CPU to Communicate Via SMBus
  Slave Interface Allows External SMBus Master to Control Resume Events
Real-Time Clock
  256-byte Battery-Back CMOS SRAM
  Includes Date Alarm
  Two 8-byte Lockout Ranges
Microsoft Win95* Compliant
324 mBGA Package
  Suspend and Resume Logic
  Supports Thermal Alarm
  Support for External Microcontroller
  Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0 Specification and OS Directed Power Management
Integrated IDE Controller
  Independent Timing of up to 4 Drives
  PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
  Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec

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