datasheetbank_Logo    Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Number :
Home  >>>  Fairchild  >>> DM74LS112A PDF

DM74LS112A Datasheet PDF - Fairchild Semiconductor

Part NumberDM74LS112A Fairchild
Fairchild Semiconductor Fairchild
DescriptionDual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
DM74LS112A Datasheet PDF : DM74LS112A pdf   
DM74LS112AN image

General Description
This device contains two independent negative-edge-trig gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Share Link : Fairchild

Other manufacturer searches related to DM74LS112A

DM74LS112A BCD To 7 Segment Decoder / Driver DM74LS112A View National ->Texas Instruments
National ->Texas Instruments  

Language : Korean   Chinese   Japanese   Russian   Spanish

@ 2014 - 2018  [ Home  ] [ Privacy Policy ] [ Request Datasheet  ] [ Contact Us ]