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DM74ALS137 Datasheet PDF - Fairchild Semiconductor

Part NameDescriptionManufacturer
DM74ALS137 3 to 8 Line Decoder/Demultiplexer with Address Latches Fairchild
Fairchild Semiconductor Fairchild
DM74ALS137 Datasheet PDF : DM74ALS137 pdf   
DM74ALS137MX image

General Description
The ALS137 is a three line to eight line decoder/demultiplexer with latches on the three address inputs. When the latch-enable input (GL) is LOW, the ALS137 acts as a decoder/demultiplexer. When GL goes from LOW-to-HIGH, the address present at the select inputs (A, B, and C) is stored in the latches. Further address changes are ignored as long as GL remains HIGH. The output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are HIGH unless G1 is HIGH and G2 is LOW. The ALS137 is ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

■ Combines decoder and 3-bit address latch
■ Incorporates 3 enable inputs to simplify cascading
■ Low power dissipation: 28 mW typ
■ Switching specifications guaranteed over full temperature and VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process

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