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74F112 Datasheet PDF - Fairchild Semiconductor

Part Name
Description
Manufacturer
74F112
Fairchild
Fairchild Semiconductor Fairchild
Other PDF
  no available.
PDF
74F112 Datasheet PDF : 74F112 pdf     
74F112 image

General Description
The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.
Simultaneous LOW signals on SD and CD force both Q and Q HIGH.

Asynchronous Inputs:
   LOW input to SD sets Q to HIGH level
   LOW input to CD sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH

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Part Name
Description
PDF
Manufacturer
Dual JK Negative Edge-Triggered Flip-Flop
Hitachi -> Renesas Electronics
Dual JK negative edge-triggered flip-flop
Motorola => Freescale
Dual JK Negative Edge-Triggered Flip-Flop
AVG Semiconductors=>HITEK
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY
Motorola => Freescale
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale
Dual JK negative edge-triggered flip-flop
Motorola => Freescale
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Motorola => Freescale

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