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HM5259165B-75 Datasheet PDF - Elpida Memory, Inc

Part NameDescriptionManufacturer
HM5259165B-75 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM Elpida
Elpida Memory, Inc Elpida
Other PDF  no available.
HM5259165B-75 Datasheet PDF : HM5259165B-75 pdf   
HM5259805BTD-A6 image

Description
The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.

Features
• 3.3 V power supply
• Clock frequency: 133 MHz/100 MHz (max)
• LVTTL interface
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8
• 2 variations of burst sequence
- Sequential (BL = 1/2/4/8)
- Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5259805B/HM5259405B)
                               : DQMU/DQML (HM5259165B)
• Refresh cycles: 8192 refresh cycles/32 ms
• 2 variations of refresh
- Auto refresh
- Self refresh

 

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