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HB52RD648DC-B Datasheet PDF - Elpida Memory, Inc

Part NameDescriptionManufacturer
HB52RD648DC-B 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword × 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M × 8 components) PC133/100 SDRAM Elpida
Elpida Memory, Inc Elpida
Other PDF  no available.
HB52RD648DC-B Datasheet PDF : HB52RD648DC-B pdf   
HB52RD648DC-B image

Description
The HB52RF648DC, HB52RD648DC are a 32M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 16 pieces of 256-Mbit SDRAM (HM5225805BTB) sealed in TCP package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the products is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, they make high density mounting possible without surface mount technology. They provide common data inputs and outputs. Decoupling capacitors are mounted beside TCP on the module board.

Features
• Fully compatible with: JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
    - Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
    - Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 133/100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8
• 2 variations of burst sequence
    - Sequential
    - Interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64 ms
• 2 variations of refresh
    - Auto refresh
    - Self refresh
• Low self refresh current: HB52RF648DC-xxBL (L-version) : HB52RD648DC-xxBL (L-version)

 

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