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T-8208-BAL-DB Datasheet PDF - Agere -> LSI Corporation

Part NameDescriptionManufacturer
T-8208-BAL-DB CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8208-BAL-DB Datasheet PDF : T-8208-BAL-DB pdf   
T8208-BAL-DB image

The CelXpres T8208 device integrates all of the required functionality to transport ATM cells across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface.
The T8208 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 635 Mbits/s. The T8208 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum’s level 2 specification. The T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 interface configuration. With four transmit cells available/enable (TxCLAV/Enb*) pairs of signals and receive cell available/enable (RxCLAV/Enb*) pairs of signals, 64 MPHYs can be supported. For a 16-bit UTOPIA 2 interface configuration, the T8208 supports MPHY operation with one transmit cell available (TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 8 PHY ports. With four transmit cell available (TxCLAV/Enb*) signals and four receive cell available (RxCLAV/Enb*) signals, 32 MPHYs can be supported in 16-bit UTOPIA 2 interface configuration. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided.

■ OC-12 data throughput on UTOPIA (16-bit)
   (independently on RX and TX UTOPIA)
■ Shared UTOPIA mode
■ UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level handshake interface (ATM or PHY layers)
■ Multi-PHY (MPHY) operation
■ Programmable ATM layer supports up to 64 PHY ports
■ Egress SDRAM buffer support to extend UTOPIA output priority queues for 32K to 512K cells:
   — 128 queues configurable up to four queues per PHY with programmable sizes
   — Programmable number of UTOPIA output queues with four levels of priority
■ Support of ATM traffic management via partial
   packet discard (PPD), forward explicit congestion
   notification (FECN), and the cell loss priority (CLP) bit
■ Programmable slew rate GTL+ I/O:
   — Programmable as bus arbiter
   — 1.7 Gbits/s cell bus operation
■ Flexible per port cell counters
■ Cell header insertion with virtual path identifier
   (VPI) and virtual channel identifier (VCI) translation
   via external SRAM (up to 64K entries)
■ Support of network node interface (NNI) and user
   network interface (UNI) header types with optional
   generic flow-control (GFC) insertion
■ Optional sourcing of cell bus clocks from device
■ LUT bypass option
■ TX UTOPIA cell buffer increased to 256 cells for better queue management with SDRAM queue bypass option
■ Ability for cell bus arbiter to mask devices on the cell bus
■ Ability to modify cell bus priority based on RX PHY FIFO thresholds
■ Programmable priority for control/data cells transmission onto cell bus
■ Microprocessor access to all headers of control cell
■ Ability to clear counters on read
■ Simplified looping to any system device with a single register programming
■ UTOPIA clock sourcing with additional settings
■ Programmable operations and maintenance and resource management (OAM/RM) cell routing
■ Support of multicast and broadcast cells per PHY
■ Optional monitoring of misrouted cells
■ Counters for dropped cells per queue
■ Digital loopback before cell bus
■ Microprocessor interface, supporting both Motorola® and Intel® modes (multiplexed and nonmultiplexed)
■ Control cell transmission and reception through microprocessor port
■ Single 3.3 V power supply
■ 3.3 V TTL I/O (5 V tolerant)
■ 272-pin plastic ball grid array (PBGA) package
■ Industrial temperature range (–40 °C to +85 °C)
■ Hot insertion capability
■ Eight GPIO pins
■ JTAG support
■ Compatible with Transwitch CellBus®

■ Asymmetric digital subscriber line (ADSL) digital
   subscriber line access multiplexers (DSLAMs)
■ Access gateways
■ Access multiplexers/concentrators
■ Multiservice platforms

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