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T-8207-BAL-DB Datasheet PDF - Agere -> LSI Corporation

Part NameDescriptionManufacturer
T-8207-BAL-DB CelXpres™ ATM Interconnect Agere
Agere -> LSI Corporation Agere
T-8207-BAL-DB Datasheet PDF : T-8207-BAL-DB pdf   
T8208-BAL-DB image

The CelXpres T8207 device integrates all of the required functionality to transport ATM cells across a backplane architecture with high-speed cell traffic exceeding 1.5 Gbits/s to a maximum of 32 destinations. The management of multiple service categories and monitoring of performance on ATM and PHY interfaces is incorporated in the device’s functionality. Traffic delivery to multi-PHYs (MPHYs) is managed through the UTOPIA interface.
The T8207 device meets the ATM Forum’s universal test and operations PHY interface for ATM (UTOPIA) Level 1, Version 2.01 and Level 2, Version 1.0 specifications for cell-level handshake and MPHY data path operation with rates up to 353 Mbits/s. The T8207 supports the required MPHY operation as described in Sections 4.1 and 4.2 of the ATM Forum’s Level 2 specification. The T8207 supports MPHY operation with one transmit cell available
(TxCLAV) signal and one receive cell available (RxCLAV) signal for up to 16 PHY ports for an 8-bit UTOPIA 2 interface configuration. With two transmit cells available/enable (TxCLAV/enb*) pairs of signals and receive cells avail able/enable (RxCLAV/enb*) pairs of signals, 32 MPHYs can be supported. In addition to the required UTOPIA signals, the optional transmit parity (TxPRTY) and receive parity (RxPRTY) signals are provided.

■ > OC-3 transport capability
■ UTOPIA level 1 and 2 (8-bit) cell-level handshake
   interface (ATM or PHY layers)
■ 32 multi-PHY (MPHY) operation
■ Shared UTOPIA mode
■ Egress SDRAM buffer support to expand UTOPIA output priority queues for 32K to 512K cells:
   — 64 queues configurable up to four queues per PHY with programmable sizes
   — Programmable number of UTOPIA output queues with four levels of priority
■ Support of ATM traffic management via partial
   packet discard (PPD), forward explicit congestion
   notification (FECN), and the cell loss priority (CLP) bit
■ Programmable slew rate GTL+ I/O:
   — 1.7 Gbits/s cell bus operation
   — Programmable as bus arbiter
■ Flexible per port cell counters
■ Cell header translation and insertion with virtual
   path identifier (VPI) and virtual channel identifier
   (VCI) via external SRAM (up to 64K entries)
■ Support of network node interface (NNI) and user
   network interface (UNI) header types with optional
   generic flow control (GFC) insertion
■ Programmable operations and maintenance and
   resource management (OAM/RM) cell routing
■ Support of multicast and broadcast cells per PHY
■ Programmable priority for control/data cells trans mission onto cell bus
■ Eight GPIO pins
■ JTAG support
■ Optional monitoring of misrouted cells
■ Microprocessor interface, supporting both
   Motorola® and Intel® modes (multiplexed and nonmultiplexed)
■ Control cell transmission and reception through microprocessor port
■ Single 3.3 V power supply
■ 3.3 V TTL I/O (5 V tolerant)
■ 272-pin PBGA package
■ Industrial temperature range (–40 °C to +85 °C)
■ Hot insertion capability
■ Compatible with Transwitch CellBus®

■ Asymmetric digital subscriber line (ADSL) digital
   subscriber line access multiplexer (DSLAMs)
■ Access gateways
■ Access multiplexers/concentrators
■ Multiservice access equipment platforms

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