The ADS8608A8Aare four-bank Synchronous DRAMsorganized as 8,388,608 words x8 bitsx4 banks.
Synchronous design allowsprecise cycle control with the use of system clock I/Otransactions are possible on everyclock cycle.
•JEDECstandard LVTTL3.3V power supply
•MRS Cycle with address keyprograms
-CAS Latency(2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of the system clock
•Burst Read single write operation
•Auto & Self refresh
•8192 Refresh Cycles
•Package:54-pins 400 mil TSOP-Type II