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Part Name(s) : M4-192 M4-32/32-12VI48 M4-64/32-10VC48 M4-64/32-10VI48 M4-64/32-12VC48 M4-64/32-12VI48 M4-64/32-14VI48 M4-64/32-15VC48 M4-64/32-18VI48 M4-64/32-7VC48 M4-96/96-20YI Lattice
Lattice Semiconductor
Description : MACH 4 CPLD Family High Performance E2CMOS® IN-SYSTEM PROGRAMMABLE Logic View

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex PROGRAMMABLE Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V IN-SYSTEM PROGRAMMABLE through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% pin-out retention
◆ High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — PROGRAMMABLE polarity
   — Reset/ preset swapping
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG IN-SYSTEM programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — PROGRAMMABLE security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for IN-SYSTEM programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Part Name(s) : XC9572 XC9572-10BPQ100I XC9572-10PC44 XC9572-10PC44C XC9572-10PC44I XC9572-10PC84C XC9572-10PC84I XC9572-10PQ100C XC9572-10PQ100I XC9572-10TQ100C XC9572-10TQ100I XC9572-15BPQ100I XC9572-15P XC9572-15PC44C XC9572-15PC44I XC9572-15PC84C XC9572-15PC84I XC9572-15PCG44C XC9572-15PQ100C XC9572-15PQ100I XC9572-15TQ100C XC9572-15TQ100I XC9572-7BPQ100C XC9572-7BPQ100I XC9572-7PC44C Xilinx
Xilinx Inc
Description : XC9536 IN-SYSTEM PROGRAMMABLE CPLD View

Description
The XC9572 is  a high-performance CPLD  providing advanced IN-SYSTEM programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure2for the architecture overview.

Features
•  7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
•  72 macrocells with 1,600 usable gates
•  Up to 72 user I/O pins
•  5 V IN-SYSTEM PROGRAMMABLE (ISP)
-  Endurance of 10,000 program/erase cycles
-  Program/erase over full commercial voltage and temperature range
•  Enhanced pin-locking architecture
•  Flexible 36V18 Function Block
-  90 product terms drive any or all of 18 macrocells within Function Block
-  Global and product term clocks, output enables, set and reset signals
•  Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
•  PROGRAMMABLE power reduction mode in each macrocell
•  Slew rate control on individual outputs
•  User PROGRAMMABLE ground pin capability
•  Extended pattern security features for design protection
•  High-drive 24 mA outputs
•  3.3 V or 5 V I/O capability
•  Advanced CMOS 5V FastFLASH technology
•  Supports parallel programming of more than one XC9500 concurrently
•  Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages

Part Name(s) : PSD4135G2U PSD4135G2V PSD4235G2_02 ST-Microelectronics
STMicroelectronics
Description : Flash IN-SYSTEM-PROGRAMMABLE Peripherals for 16-Bit MCUs View

Introduction
The PSD4000 series of PROGRAMMABLE Microcontroller (MCU) Peripherals brings IN-SYSTEM-Programmability (ISP) to Flash memory and PROGRAMMABLE logic. The result is a simple and flexible solution for embedded designs. PSD4000 devices combine many of the peripheral functions found in MCU based applications:
   • 4 Mbit of Flash memory
   • A secondary Flash memory for boot or data
   • Over 3,000 gates of Flash PROGRAMMABLE logic
   • 64 Kbit SRAM
   • Reconfigurable I/O ports
   • PROGRAMMABLE power management.
  
FEATURES SUMMARY
■ 5 V±10% Single Supply Voltage:
■ Up to 4 Mbit of Primary Flash Memory (8 uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform sectors)
■ Up to 64 Kbit SRAM
■ Over 3,000 Gates of PLD: DPLD and CPLD
■ 52 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
■ PROGRAMMABLE power management
■ High Endurance:
   – 100,000 Erase/Write Cycles of Flash Memory
   – 1,000 Erase/Write Cycles of PLD

Part Name(s) : LC4256C-10FN256BI1 Lattice
Lattice Semiconductor
Description : 3.3V/2.5V/1.8V IN-SYSTEM PROGRAMMABLE SuperFAST High density PDLs View

The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families, the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family.

Features
■ High Performance
    • fMAX = 400MHz maximum operating frequency
    • tPD = 2.5ns propagation delay
    • Up to four global clock pins with PROGRAMMABLE clock polarity control
    • Up to 80 PTs per output
■ Ease of Design
    • Enhanced macrocells with individual clock, reset, preset and clock enable controls
    • Up to four global OE controls
    • Individual local OE control per I/O pin
    • Excellent First-Time-FitTM and refit
    • Fast path, SpeedLockingTM Path, and wide-PT path
    • Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
■ Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)
    • Typical static current 10µA (4032Z)
    • Typical static current 1.3mA (4000C)
    • 1.8V core low dynamic power
    • ispMACH 4000Z operational down to 1.6V VCC
■ Broad Device Offering
    • Multiple temperature range support
        – Commercial: 0 to 90°C junction (Tj)
        – Industrial: -40 to 105°C junction (Tj)
        – Automotive: -40 to 130°C junction (Tj)
■ Easy System Integration
    • Superior solution for power sensitive consumer applications
    • Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
    • Operation with 3.3V (4000V), 2.5V (4000B) or 1.8V (4000C/Z) supplies
    • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
    • Hot-socketing
    • Open-drain capability
    • Input pull-up, pull-down or bus-keeper
    • PROGRAMMABLE output slew rate
    • 3.3V PCI compatible
    • IEEE 1149.1 boundary scan testable
    • 3.3V/2.5V/1.8V IN-SYSTEM PROGRAMMABLE (ISP™) using IEEE 1532 compliant interface
    • I/O pins with fast setup path
    • Lead-free package options


Part Name(s) : ATMEGA261 Atmel
Atmel Corporation
Description : 8-bit Microcontroller with 2/4/8K Bytes IN-SYSTEM PROGRAMMABLE Flash View

8-bit Microcontroller with 2/4/8K Bytes IN-SYSTEM PROGRAMMABLE Flash

Part Name(s) : ICS94211 ICS94211F-T AV94211 AV94211F-T ICST
Integrated Circuit Systems
Description : PROGRAMMABLE System Frequency Generator for PII/III? View

General Description
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system.

Features:
• PROGRAMMABLE ouput frequency.
• PROGRAMMABLE ouput rise/fall time.
• PROGRAMMABLE PCICLK, PCICLK_F, SDRAM skew.
• Real time system reset output
• Spread spectrum for EMI control typically by 7dB to 8dB, with PROGRAMMABLE spread percentage.
• Watchdog timer technology to reset system if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select

Output Features:
• 2 - CPUs @2.5V
• 1 - IOAPIC @ 2.5V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.

Recommended Application:
    440BX/VIA Apollo Pro133/ ALI 1631 style chipset.

Part Name(s) : PSD813F1A-12J PSD813F1A-12JI PSD813F1A-12M PSD813F1A-12MI PSD813F1A-12U PSD813F1A-12UI PSD813F1A-70J PSD813F1A-70JI PSD813F1A-70M PSD813F1A-70MI PSD813F1A-70U PSD813F1A-70UI PSD813F1A-90J PSD813F1A-90JI PSD813F1A-90M PSD813F1A-90MI PSD813F1A-90U PSD813F1A-90UI PSD813F1A-70JT PSD813F1A-70JIT PSD813F1A-70MT PSD813F1A-70MIT PSD813F1A-70UT PSD813F1A-70UIT PSD813F1A-90JT ST-Microelectronics
STMicroelectronics
Description : Flash IN-SYSTEM PROGRAMMABLE (ISP) Peripherals for 8-bit MCUs, 5V View

SUMMARY DESCRIPTION
The PSD family of PROGRAMMABLE Microcontroller (MCU) Peripherals brings IN-SYSTEM Programmability (ISP) to Flash memory and PROGRAMMABLE logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

FEATURES SUMMARY
■ DUAL BANK FLASH MEMORIES
    – 1 Mbit of Primary Flash Memory (8 Uniform Sectors)
    – 256 Kbit Secondary EEPROM (4 Uniform Sectors)
    – Concurrent operation: read from one memory while erasing and writing the other
■ 16 Kbit SRAM (BATTERY-BACKED)
■ PLD WITH MACROCELLS
    – Over 3,000 Gates Of PLD: DPLD and CPLD
    – DPLD - User-defined Internal chip-select decoding
    – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
■ 27 RECONFIGURABLE I/Os
    – 27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; and Special function I/Os.
    Note: 16 of the I/O ports may be configured as open-drain outputs.
■ ENHANCED JTAG SERIAL PORT
    – Built-in JTAG-compliant serial port allows full-chip IN-SYSTEM Programmability (ISP)
    – Efficient manufacturing allows for easy product testing and programming
■ PAGE REGISTER
    – Internal page register that can be used to expand the microcontroller address space by a factor of 256.
■ PROGRAMMABLE POWER MANAGEMENT
■ HIGH ENDURANCE:
– 100,000 Erase/WRITE Cycles of Flash Memory
– 10,000 Erase/WRITE Cycles of EEPROM
– 1,000 Erase/WRITE Cycles of PLD
– Data Retention: 15-year minimum at 90°C (for Main Flash, Boot, PLD and Configuration bits).
■ SINGLE SUPPLY VOLTAGE:
    – 5V±10% for 5V
■ STANDBY CURRENT AS LOW AS 50µA

Part Name(s) : PSD813F1AV-12J PSD813F1AV-12JI PSD813F1AV-12M PSD813F1AV-12MI PSD813F1AV-12U PSD813F1AV-12UI PSD813F1AV-70J PSD813F1AV-70JI PSD813F1AV-70M PSD813F1AV-70MI PSD813F1AV-70U PSD813F1AV-70UI PSD813F1AV-90J PSD813F1AV-90JI PSD813F1AV-90M PSD813F1AV-90MI PSD813F1AV-90U PSD813F1AV-90UI PSD813F1AV-70JT PSD813F1AV-70JIT PSD813F1AV-70MT PSD813F1AV-70MIT PSD813F1AV-70UT PSD813F1AV-70UIT PSD813F1AV-90JT ST-Microelectronics
STMicroelectronics
Description : Flash IN-SYSTEM PROGRAMMABLE (ISP) Peripherals for 8-bit MCUs, 3.3V View

SUMMARY DESCRIPTION
The PSD family of PROGRAMMABLE Microcontroller (MCU) Peripherals brings IN-SYSTEM Programmability (ISP) to Flash memory and PROGRAMMABLE logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.

FEATURES SUMMARY
■ DUAL BANK FLASH MEMORIES
    – 1 Mbit of Primary Flash Memory (8 Uniform Sectors)
    – 256 Kbit Secondary EEPROM (4 Uniform Sectors)
    – Concurrent operation: read from one memory while erasing and writing the other
■ 16 Kbit SRAM (BATTERY-BACKED)
■ PLD WITH MACROCELLS
    – Over 3,000 Gates Of PLD: DPLD and CPLD
    – DPLD - User-defined Internal chip-select decoding
    – CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
■ 27 RECONFIGURABLE I/Os
    – 27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; and Special function I/Os.
    Note: 16 of the I/O ports may be configured as open-drain outputs.
■ ENHANCED JTAG SERIAL PORT
    – Built-in JTAG-compliant serial port allows full-chip IN-SYSTEM Programmability (ISP)
    – Efficient manufacturing allows for easy product testing and programming
■ PAGE REGISTER
    – Internal page register that can be used to expand the microcontroller address space by a factor of 256.
■ PROGRAMMABLE POWER MANAGEMENT
■ HIGH ENDURANCE:
    – 100,000 Erase/WRITE Cycles of Flash Memory
    – 10,000 Erase/WRITE Cycles of EEPROM
    – 1,000 Erase/WRITE Cycles of PLD
    – Data Retention: 15-year minimum at 90°C (for Main Flash, Boot, PLD and Configuration bits).
■ SINGLE SUPPLY VOLTAGE:
    – 3.3V±10% for PSD813F1V
■ STANDBY CURRENT AS LOW AS 50µA

Part Name(s) : PSD913 PSD913F PSD913F3-B ST-Microelectronics
STMicroelectronics
Description : Flash IN-SYSTEM PROGRAMMABLE (ISP) peripherals for 8-bit MCUs, 90ns View

The PSD9XX family of PROGRAMMABLE System Devices (for 8-bit microcontrollers) brings IN-SYSTEM-Programmability (ISP) to Flash memory and PROGRAMMABLE logic.

The result is a simple and flexible solution for embedded designs. PSD9XX devices combine many of the peripheral functions found in MCU based applications:
• Up to 2 Mbit of Flash memory
• A secondary 256 Kbit Flash memory
• Over 2,000 gates of Flash PROGRAMMABLE logic
• Up to 256 Kbit SRAM
• Reconfigurable I/O ports
PROGRAMMABLE power management.

■ Single Supply Voltage:
– 5 V±10% for PSD9xxF2
– 3.3 V±10% for PSD9xxF2-V
■ Up to 2Mbit of Primary Flash Memory (8 uniform sectors)
■ 256Kbit Secondary Flash Memory (4 uniform sectors)
■ Up to 256Kbit SRAM
■ Over 2,000 Gates of PLD: DPLD
■ 27 Reconfigurable I/O ports
■ Enhanced JTAG Serial Port
■ PROGRAMMABLE power management
■ High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 1,000 Erase/Write Cycles of PLD

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