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Part Name(s) : STP1010 STP1010TAB-50 ETC
Unspecified
Description : MicroSPARC, Highly Integrated 32-BIT RISC MICROPROCESSOR View

[Sun]

MicroSPARC, Highly Integrated 32-BIT RISC MICROPROCESSOR

Part Name(s) : TS68000 TS68000CP8 TS68000VP8 TS68000CFN8 TS68000CP10 TS68000CP12 TS68000CP16 TS68000CR10 TS68000CR12 TS68000CR16 TS68000VFN8 TS68000VP10 TS68000CFN10 TS68000CFN16 TS68000VFN12 ST-Microelectronics
STMicroelectronics
Description : HMOS 16/32-BIT MICROPROCESSOR View

HMOS 16/32-BIT MICROPROCESSOR

Part Name(s) : MC68030 MC68030FE20 MC68030FE25 MC68030FE33 MC68030RC20 MC68030RC25 MC68030RC33 Motorola
Motorola => Freescale
Description : ENHANCED 32-BIT MICROPROCESSOR View

INTRODUCTION
The MC68030 is a second-generation full 32-BIT enhanced MICROPROCESSOR from Motorola.
The MC68030 is a member of the M68000 Family of devices that combines a central processing unit (CPU) core, a data cache, an instruction cache, an enhanced bus controller, and a memory management unit (MMU) in a single VLSI device. The processor is designed to operate at clock speeds beyond 20 MHz. The MC68030 is implemented with 32-BIT registers and data paths, 32-BIT addresses, a rich instruction set, and versatile addressing modes.
The MC68030 is upward object code compatible with the earlier members of the M68000 Family and has the added features of an on-chip MMU, a data cache, and an improved bus interface. It retains the flexible coprocessor interface pioneered in the MC68020 and provides full IEEE floating-point support through this interface with the MC68881 or MC68882 floating-point coprocessor. Also, the internal functional blocks of this MICROPROCESSOR are designed to operate in parallel, allowing instruction execution to be overlapped. In addition to instruction execution, the internal caches, the on-chip MMU, and the external bus controller all operate in parallel.

FEATURES
The features of the MC68030 MICROPROCESSOR are:
• Object Code Compatible with the MC68020 and Earlier M68000 MICROPROCESSORs
• Complete 32-BIT Nonmultiplexed Address and Data Buses
• 16 32-BIT General-Purpose Data and Address Registers
• Two 32-BIT Supervisor Stack Pointers and 10 Special-Purpose Control Registers
• 256-Byte Instruction Cache and 256-Byte Data Cache Can Be Accessed Simultaneously
• Paged MMU that Translates Addresses in Parallel with Instruction Execution and Internal Cache Accesses
• Two Transparent Segments Allow Untranslated Access to Physical Memory To Be Dfined for Systems That Transfer Large Blocks of Data between Predefined Physical Addresses — e.g., Graphics Applications
• Pipelined Architecture with Increased Parallelism Allows Accesses to Internal Caches To Occur in Parallel with Bus Transfers and Instruction Execution To Be Overlapped
• Enhanced Bus Controller Supports Asynchronous Bus Cycles (three clocks minimum), Synchronous Bus Cycles (two clocks minimum), and Burst Data Transfers (one clock minimum) all to the Physical Address Space
• Dynamic Bus Sizing Supports 8-, 16-, 32-BIT Memories and Peripherals
• Support for Coprocessors with the M68000 Coprocessor Interface — e.g., Full IEEE Floating-Point Support Provided by the MC68881/MC68882 Floating-Point Coprocessors
• 4-Gbyte Logical and Physical Addressing Range
• Implemented in Motorola's HCMOS Technology That Allows CMOS and HMOS (High Density NMOS) Gates to be Combined for Maximum Speed, Low Power, and Optimum Die Size
• Processor Speeds Beyond 20 MHz

 

Part Name(s) : Q67120-C494 Q67120-C517 Q67120-C552 SAB-R2000A-12-A SAB-R2000A-16-A SAB-R2000A-20-A Infineon
Infineon Technologies
Description : High Performance 32-BIT RISC MICROPROCESSOR View

High Performance 32-BIT RISC MICROPROCESSOR


Part Name(s) : UPD30550 UPD30550F2-300-NN1 UPD30550F2-400-NN1 NEC
NEC => Renesas Technology
Description : VR5500? 64-/32-BIT MICROPROCESSOR View

DESCRIPTION
The µPD30550 (VR5500) is a member of the VRSeries™ of RISC (Reduced Instruction Set Computer) MICROPROCESSORs. It is a high-performance 64-/32-BIT MICROPROCESSOR that employs the RISC architecture developed by MIPS™.
The VR5500 allowsselection of a 64-bit or 32-BIT bus width for the system interface, and can operate using protocols compatible with the VR5000 Series™ and VR5432™

. FEATURES
• MIPS 64-bit RISC architecture
• High-speed operation processing
• Two-waysuperscaler super pipeline
• 300 MHz product:  603 MIPS
  400 MHz product:  804 MIPS
• High-speed translation lookaside buffer (TLB) (48 entries)
•Address space
• Physical:  36 bits (64-bit bus selected) 32 bits (32-BIT bus selected)
• Virtual:  40 bits (in 64-bit mode) 31 bits (in 32-BIT mode)
• On-chip floating-point unit (FPU)
• Supports sum-of-products instructions
• On-chip primarycache memory (instruction/data: 32 KB each)
• 2-wayset associative
• Supports line lock feature

Part Name(s) : S3C2400 S3C2400X01 Samsung
Samsung
Description : 32-BIT RISC MICROPROCESSOR View

PRODUCT OVERVIEW

INTRODUCTION
SAMSUNGs S3C2400 16/32-BIT RISC MICROPROCESSOR is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA, System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, 8-channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPI and PLL for clock generation.
The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture) An outstanding feature of the S3C2400 is its CPU core, a 16/32-BIT ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with a 8-word line length.
By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

• 1.8V internal, 3.3V external (I/O boundary) MICROPROCESSOR with 16KB I-Cache,
   16KB D-Cache, and MMU.
• External memory controller. (EDO/SDRAM Control, Chip Select logic)
• LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA.
• 4-ch DMAs with external request pins
• 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI
• 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
• MMC interface (ver 2.11)
• 2-port USB Host /1- port USB Device (ver 1.1)
• 4-ch PWM timers & 1-ch internal timer
• Watch Dog Timer
• 90-bit general purpose I/O ports/8-ch external interrupt source
• Power control: Normal, Slow, Idle, Stop and SL_IDLE mode
• 8-ch 10-bit ADC.
• RTC with calendar function.
• On-chip clock generator with PLL

Part Name(s) : MC68EC030 Freescale
Freescale Semiconductor
Description : Second-Generation 32-BIT Enhanced Embedded Controller View

The MC68EC030 is a 32-BIT embedded controller that streamlines the functionality of an MC68030 for the requirements of embedded control applications.  The MC68EC030 is optimized to maintain
performance while using cost-effective memory subsystems. The rich instruction set and  addressing mode capabilities of the MC68020, MC68030, and MC68040 have been maintained, allowing a clear migration path for M68000 systems. The main features of the MC68EC030 are as follows:
•  Object-Code Compatible with the MC68020, MC68030, and Earlier M68000 MICROPROCESSORs
• Burst-Mode Bus Interface for Efficient DRAM Access
• On-Chip Data Cache (256 Bytes) and On-Chip Instruction Cache (256 Byte)
• Dynamic Bus Sizing for Direct Interface to 8-, 16-, and 32-BIT Devices
• 25- and 40-MHz Operating Frequency (up to 9.2 MIPS)
• Advanced Plastic Pin Grid Array Packaging for Through-Hole Applications

Part Name(s) : TS68020MF1B TS68020MFB TS68020MR1B TS68020MRB TS68020VF1B TS68020VR1B Atmel
Atmel Corporation
Description : HCMOS 32-BIT Virtual Memory MICROPROCESSOR View

Description
The TS68020 is the first full 32-BIT implementation of the TS68000 family of MICROPROCESSORs. Using HCMOS technology, the TS68020 is implemented with 32-BIT registers and data paths, 32-BIT addresses, a rich instruction set, and versatile addressing modes.

Features
• Object Code Compatible with Earlier TS68000 MICROPROCESSORs
• Addressing Mode Extensions for Enhanced Support of High Level Languages
• New Bit Field Data Type Accelerates Bit-oriented Application, i.e. Video Graphics
• Fast on-chip Instruction Cache Speed Instructions and Improves Bus Bandwidth
• Co-processor Interface to Companion 32-BIT Peripherals: TS68881 and TS68882 Floating Point Co-processors
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions to be Executed Concurrently
• High Performance Asynchronous Bus in Non-multiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-, 16-, 32-BIT Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-BIT General-purpose Data and Address Registers
• Two 32-BIT Supervisor Stack Pointers and 5 Special Purpose Control Registers
• 18 Addressing Modes and 7 Data Types
• 4-Gbyte Direct Addressing Range
• Processor Speed: 16.67 MHz - 20 MHz - 25 MHz
• Power Supply: 5.0 VDC ± 10%

Part Name(s) : UPD70741GC-25-7EA UPD70741GC-25-8EU NEC
NEC => Renesas Technology
Description : V821? 32-/16-BIT MICROPROCESSOR View

The µPD70741 (V821) is a 32/16-bit RISC MICROPROCESSOR that uses, as its processor core, the highperformance 32-BIT MICROPROCESSOR µPD70732 (V810TM) designed for built-in control applications. It incorporates peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller.

FEATURES
● The V810 32-BIT MICROPROCESSOR is used as the CPU core
    • Separate address/data bus
        Address bus : 24 bits
        Data bus : 16 bits
    • Built-in 1-Kbyte instruction cache memory
    • Pipeline structure of 1-clock pitch
    • Internal 4-Gbyte linear address space
    • 32-BIT general-purpose registers: 32
● Instructions ideal for various application fields
    • Floating-point operation instructions and bit string instructions
● Interrupts controller
    • Nonmaskable : 1 external input
    • Maskable : 8 external inputs and 11 types of internal sources
    • Priorities can be specified in units of four groups.
● Wait control unit
    • Capable of CS control over four blocks in both memory and I/O spaces.
    • Linear address space of each block: 16M bytes
● Memory access control functions
    • Supports DRAM high-speed page mode.
    • Supports page-ROM page mode.
● DMA controller (DMAC): 2 channels
    • Maximum transfer count: 65 536
    • Two transfer types (fly-by (1-cycle) transfer and 2-cycle transfer)
    • Three transfer modes (single transfer, singlestep transfer, and block transfer)
● Serial interfaces : 2 channels
    • Asynchronous serial interface (UART): 1 channel
    • Synchronous serial interface (CSI): 1 channel
● Real-time pulse unit
    • 16-bit timer/event counter : 1 channel
    • 16-bit interval timer : 1 channel
● Watchdog timer functions
● Clock generator functions
● Standby functions (HALT, IDLE, and STOP modes)

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