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Description : Keyboard and embedded Controller for Notebook PC

Description
The MEC1310 is a 128-pin 3.3V LPC-based ACPI 2.0 and PC99/PC2001 compliant Notebook I/O Controller. See FIGURE 1: MEC1310 Block Diagram on page 4. The MEC1310 incorporates a high-performance 8051-based keyboard and system controller with internal embedded 64K SRAM; a 1K byte Boot ROM, and 64-bytes battery backed registers. The embedded 64K SRAM is loaded via HOST/8051 SPI Memory Interface. The HOST/8051 SPI Memory Interface can be configured in Switched SPI Flash Configuration or Parallel Shared SPI Flash Configuration.
The MEC1310 has four PS/2 ports; an 16C550A-compatible 2 pin UART for Debug Port; three 8584-style I2C/SMBus controllers with two selectable ports per controller; a Serial IRQ peripheral agent interface; three ACPI embedded Controller Interface; General Purpose I/O pins and seven General Purpose Outputs; four independently programmable pulse width modulators; dual fan control through The implementation of two fan tachometer input pins, RPM-PWM block with one tachometer input and one PWM output; hardware monitoring of a PWM input and maskable hardware wake up events; one BC-Link Combined High Speed/Low Speed Bus Master Controller; 5 channel Analog to Digital Converter.
The MEC1310 has two separate power planes to provide “instant on” and system power management functions. Additionally, The MEC1310 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. Wake-up events and ACPI-related functions are supported through The SCI Interface.

Product Features
• 3.3V Operation with 5V Tolerant Buffers on PS/2 pins
• ACPI 1.0/2.0 PC99/PC2001 Compliant
• LPC Interface with Clock Run Support
   - Supports LPC Bus frequencies of 19.2MHz to 33MHz
   - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
   - 15 Direct IRQs
   - ACPI SCI Interface
   - nSMI output and supporting PM registers
   - Shadowed write only registers
• Internal 64K SRAM in MEC1310
   - Loaded at VCC1 power from The HOST/8051 SPI Memory Interface
   - Provides 64KB of 8051 program space
   - 32k-Byte region shared with 8051data space
• HOST/8051 SPI Memory Interface
   - 3-pin Full Duplex serial communication interface.
   - One Chip Select Pins
   - Fully 8051 Controlled
   - Hardware Support for two SPI Flash Configu rations:
      – Switched SPI Flash Configuration
      – Parallel Shared SPI Flash Configuration
      – Debug Programming Interface
• Two Power Planes
   - Low Standby Current in Sleep Mode
• Three ACPI embedded Controller Interface
• Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a)
• High-Performance embedded 8051 Keyboard and System Controller
   - Provides System Power Management
   - System Watch Dog Timer (WDT)
   - 8042 Style Host Interface
   - Supports Interrupt and Polling Access
   - 1024 Boot /ROM
   - 256 Bytes Data RAM
   - On-Chip Memory-Mapped Control Registers
   - Access to VCC0 Backed Registers
   - Up to 18x8 Keyboard Scan Matrix
   - Two 16-Bit Timer/Counters
   - Integrated Full-Duplex Serial Port Interface
   - Seventy-Three 8051 Interrupt Sources
   - Thirty-Two 8-Bit, Host/8051 Mailbox Registers
   - Sixty-Four Maskable Hardware Wake-Up Events
   - Fast GATEA20
   - Fast CPU_RESET
   - Multiple Clock Sources and Operating Fre quencies
   - IDLE and SLEEP Modes
   - Trace FIFO Debug Port
• Accurate Fail-Safe Ring Oscillator
   - Single Clock source for most 8051 and SIO functions
   - Provides 2% frequency accuracy
   - Lock Bit provides status
   - 32.768KHz-input clock
   – Single ended input
   – Compatible with south bridge SUSCLK/ RSMRST# gating rules
   – replacement 32K distribution available when RSMRST# is asserted
   – Very low power state with only external 32K clock distributed
• Integrated Standby Power Reset Generator
   - VCC1_RST# open drain output
   - Accepts External driven Reset
• VCC0 Backed Resources
   - 64 Byte VCC0 Backed Registers
   - VCC0 Backed Status Register
• Three 8584-Style I2C/SMBus Controllers
   - 8051 Controlled Logic Allows I2C/SMBus Master or Slave Operation
   - I2C/SMBus Controllers are Fully Operational on Standby Power
   - Two Controllers with 2 Sets of Dedicated Pins per I2C/SMBus Controller
   - One Controller with one Set of Dedicated Pins per I2C/SMBus Controller
• Four independent Hardware Driven PS/2 Ports
   - GPIO signal function associated with each pin
• PECI Interface 2.0  (Continue....)

Part Name(s) : MTV512MV MTV512M
Myson
Myson Century Inc
Description : 8051 embedded Monitor Controller 64K Flash Type

GENERAL DESCRIPTIONS
The MTV512M micro-controller is an 8051 CPU core embedded device especially tailored for flat panel display applications. It includes an 8051 CPU core, 768-byte SRAM, 4 channels of 6-bit ADC, 3 external counters/timers, 6 channels of PWM DAC, VESA DDC interface, and a 64K-byte internal program Flash-ROM memory in 44-pin PLCC package.

FEATURES
8051 core, 12MHz operating frequency with single/double CPU clock option
• 0.35um process; 3.3V power supply
• 768-byte RAM; 64K-byte program Flash memory
• Maximum 6 channels of PWM DAC
• Compliant with VESA DDC1/2B/2Bi/2B+ standard
• Dual slave IIC addresses; two H/W auto transfer DDC1/DDC2x data for both D-sub and DVI interfaces
• Watchdog timer with programmable interval
• Support external counters/timers, 1 & 2
• Single/double frequency clock output
• Two external interrupts, INT1 is shared with Slave IIC interrupt source.
• Maximum 4 channels of 6-bit ADC
• Flash-ROM code protection selection
• 44-pin PLCC package

SMSC
SMSC -> Microchip
Description : Legacy-Free Keyboard/embedded Controller with SPI and LPC Docking Interface

General Description
The LPC47N350 is a highly integrated LPC-based ACPI 2.0 and PC2001 compliant Keyboard, System, and Power Management Controller for Notebook PC Applications. See Figure 1.1.
The LPC47N350 incorporates a high-performance 8051-based keyboard and system controller with internal 64k byte Flash ROM; a hot-plug Docking LPC port; a Serial Peripheral Interface (SPI), four PS/2 ports; a real-time clock; a 16C550A-compatible 2 pin UART for Debug Port; two 8584-style I2C/SMBus controllers with two selectable ports per controller; a Serial IRQ peripheral agent interface; an ACPI embedded Controller Interface; forty-one General Purpose I/O pins; four independently programmable pulse width modulators; dual fan control through The implementation of two fan tachometer input pins; and maskable hardware wake-up events.

Product Features
■ 3.3V Operation with 5V Tolerant Buffers
■ ACPI 2.0 PC2001 Compliant
■ LPC Interface with Clock Run Support
   — Decode I/O, Memory, and FWH cycles
   — Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
   — 15 Direct IRQs
   — ACPI SCI Interface
   — nSMI output and supporting PM registers
   — Shadowed write only registers
■ LPC Switching
   — Hot Plug LPC Docking Interface
   — Secondary Switchable LPC interface (3.3V only)
■ Internal 64K Flash ROM
   — Programmed From Direct Parallel Interface, 8051, or LPC Host
   — 2k-Byte Lockable Boot Block
   — Can be Programed Without 8051 Intervention
■ Three Power Planes
   — Low Standby Current in Sleep Mode
■ ACPI embedded Controller Interface
■ Configuration Register Set Compatible with ISA Plugand-Play Standard (Version 1.0a)
■ High-Performance embedded 8051 Keyboard and System Controller
   — Provides System Power Management
   — System Watch Dog Timer (WDT)
   — 8042 Style Host Interface
   — Supports Interrupt and Polling Access
   — 512 Bytes Executable RAM
   — 512 Bytes Data RAM
   — On-Chip Memory-Mapped Control Registers
   — Access to RTC and CMOS Registers
   — Up to 16x8 Keyboard Scan Matrix
   — Two-16 Bit Timer/Counters
   — Integrated Full-Duplex Serial Port Interface
   — Eleven 8051 Interrupt Sources
   — Thirty-Two 8-Bit, Host/8051 Mailbox Registers
   — Thirty-Two Maskable Hardware Wake-Up Events
   — Fast GATEA20
   — Fast CPU_RESET
   — Multiple Clock Sources and Operating Frequencies
   — IDLE and SLEEP Modes
   — Fail-Safe Ring Oscillator
■ Real-Time Clock
   — MC146818 and DS1287 Compatible
   — 256 Bytes of Battery Backed CMOS in Two 128-Byte Banks
   — 128 Bytes of CMOS RAM Lockable in 4x32-Byte Blocks
   — 12- and 24-Hour Time Format
   — Binary and BCD Format
   — <2µA Standby Current (typ)
■ Two 8584-Style I2C/SMBus Controllers
   — 8051 Controlled Logic Allows I2C/SMBus Master or Slave Operation
   — I2C/SMBus Controllers are Fully Operational on Standby Power
   — 2 Sets of Dedicated Pins per I2C/SMBus Controller
■ Serial Peripheral Interface (SPI)
■ Four independent Hardware Driven PS/2 Ports
■ 41 General Purpose I/O Pins
   — 25 Maskable Hardware Wake-Event Capable
   — 6 Programmable Open-Drain/Push-Pull Outputs
■ Four Programmable Pulse-Width Modulator Outputs
   — Independent Clock Rates
   — 6-Bit Duty Cycle Granularity
   — Operational in both Full on and Standby modes
■ Dual Fan Tachometer Inputs
■ Debug Port (UART)
   — High-Speed 16550A-Compatible UART with 16-Byte Send/Receive FIFOs
   — Programmable Baud Rate Generator
   — Relocatable to 480 Different Base I/O Addresses
   — 15 IRQ Options
■ XNOR-Chain Test Mode
■ 128-Pin QFP and VTQFP Package

Myson
Myson Century Inc
Description : 8051 embedded Monitor Controller Flash Type with ISP

GENERAL DESCRIPTIONS
The  MTV312M  micro-controller  is  an  8051  CPU  core  embedded  device  especially  tailored  for  CRT/LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.

FEATURES
· 8051 core, 12MHz operating frequency with double CPU clock option
· 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating
· 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)
· Maximum 14 channels of PWM DAC
· Maximum 31 I/O pins
· SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
· Built-in low power reset circuit
· Built-in self-test pattern generator with four free-running timings
· Compliant with VESA DDC1/2B/2Bi/2B+ standard
· Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
· Single master IIC interface for internal device communication
· Maximum 4-channel 6-bit ADC
· Watchdog timer with programmable interval
· Flash-ROM program code protection selection
· 40-pin DIP, 42-pin SDIP or 44-pin PLCC package

Description : 8051 embedded Monitor Controller Flash Type with ISP

[MYSON TECHNOLOGY]

GENERAL DESCRIPTIONS
The  MTV312M  micro-controller  is  an  8051  CPU  core  embedded  device  especially  tailored  for  CRT/LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, and a 64K-byte internal program Flash-ROM.

FEATURES
· 8051 core, 12MHz operating frequency with double CPU clock option
· 0.35uM process; 5V/3.3V power supply and I/O; 3.3V core operating
· 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming (ISP)
· Maximum 14 channels of PWM DAC
· Maximum 31 I/O pins
· SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment
· Built-in low power reset circuit
· Built-in self-test pattern generator with four free-running timings
· Compliant with VESA DDC1/2B/2Bi/2B+ standard
· Dual slave IIC addresses; H/W auto transfer DDC1/DDC2x data
· Single master IIC interface for internal device communication
· Maximum 4-channel 6-bit ADC
· Watchdog timer with programmable interval
· Flash-ROM program code protection selection
· 40-pin DIP, 42-pin SDIP or 44-pin PLCC package

SMSC
SMSC -> Microchip
Description : Advanced Notebook I/O Controller with On-Board FLASH

GENERAL DESCRIPTION
The LPC47N252 is a 208-pin 3.3V LPC-based ACPI 1.1 and PC99/PC2001 compliant Notebook I/O Controller with Fast Infrared for mobile applications.

FEATURES
■ 3.3V Operation with 5V Tolerant Buffers
■ ACPI 1.1, PC99/PC2001 Compliant
■ LPC Interface with Clock Run Support
    − Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems
    − 15 Direct IRQs
    − Four 8-Bit DMA Channels
    − ACPI SCI Interface
    − nSMI
    − Shadowed write only registers
■ Internal 64K Flash ROM
    − Programmed From Direct Parallel Interface, 8051, or LPC Host
    − 2k-Byte Lockable Boot Block
    − Can be Programmed Without 8051 Intervention
■ Three Power Planes
    − Low Standby Current in Sleep Mode
    − Intelligent Auto Power Management for Super I/O
■ ACPI embedded Controller Interface
■ Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a)
■ High-Performance embedded 8051 Keyboard and System Controller
    − Provides System Power Management
    − System Watch Dog Timer (WDT)
    − 8042 Style Host Interface
    − Supports Interrupt and Polling Access
    − 256 Bytes Data RAM
    − On-Chip Memory-Mapped Control Registers
    − Access to RTC and CMOS Registers
    − Up to 16x8 Keyboard Scan Matrix
    − Two 16 Bit Timer/Counters
    − Integrated Full-Duplex Serial Port Interface
    − Eleven 8051 Interrupt Sources
    − Thirty-Two 8-Bit, Host/8051 Mailbox Registers
    − Thirty-six Maskable Hardware Wake-Up Events
    − Fast GATEA20
    − Fast CPU_RESET
    − Multiple Clock Sources and Operating Frequencies
    − IDLE and SLEEP Modes
    − Fail-Safe Ring Oscillator
■ Advanced Infrared Communications Controller (IrCC 2.0)
    − IrDA V1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support
    − Two IR Ports
    − Relocatable Base I/O Address
■ Real-Time Clock
    − MC146818 and DS1287 Compatible
    − 256 Bytes of Battery Backed CMOS in Two 128-Byte Banks
    − 128 Bytes of CMOS RAM Lockable in 4x32 Byte Blocks
    − 12 and 24 Hour Time Format
    − Binary and BCD Format
    − <2µA Standby Current (typ)
■ Two 8584-Style ACCESS.Bus Controllers
    − 8051 Controlled Logic Allows ACCESS.Bus Master or Slave Operation
    − ACCESS.Bus Controllers are Fully Operational on Standby Power
    − 2 Sets of Dedicated Pins per ACCESS.Bus Controller
■ Four independent Hardware Driven PS/2 Ports
■ 83 General Purpose I/O Pins
    − 36 Maskable Hardware Wake-Event Capable
    − 18 Programmable Open-Drain/Push-Pull Outputs
    − 16 Mapped into 8051 SFR Space
    − 24 LPC/8051-Addressable
■ Three Programmable Pulse-Width Modulator Outputs
    − Independent Clock Rates
    − 6 Bit Duty Cycle Granularity
    − VCC1 and VCC2 operation mode
■ Dual Fan Tachometer Inputs
(Continue ...)

Myson
Myson Century Inc
Description : 8051 embedded LCD Monitor Controller with Flash OSD

GENERAL DESCRIPTIONS
The MTV230M micro-controller is an 8051 CPU core embedded device specially tailored to LCD Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, OSD controller, 4 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter, a 64K-byte internal program Flash-ROM and a 9K-word internal OSD character Flash-ROM.

FEATURES
· 8051 core, 12MHz operating frequency with double CPU clock option, 3.3V power supply.
· 1024-byte RAM, 64K-byte program Flash-ROM.
· Maximum 4 channels of 5V open-drain PWM DAC.
· Maximum 32 bi-directional I/O pins.
· SYNC processor for composite separation/insertion, H/V polarity/frequency check and polarity adjustment.
· Built-in low power reset circuit.
· Compliant with VESA DDC2B/2Bi/2B+ standard.
· Dual slave IIC addresses.
· Single master IIC interface for internal device communication.
· Maximum 4-channel 6-bit ADC.
· Watchdog timer with programmable interval.
· OSD controller features:
   . Full-screen display consists of 15 (rows) by 30 (columns) characters.
   . Programmable OSD menu positioning for display screen center.
   . 512 Flash-ROM fonts, with 12x18 dot matrix, including 480 standard fonts and 32 multi-color fonts.
   . Character (per row) and window intensity control.
   . Character bordering, shadowing and blinking effect.
   . Character height control (18 to 71 lines), double height and/or width control.
   . 4 programmable windows with multi-level operation and programmable shadowing width/height/color.
· In System Programming function (ISP).
· 42-pin SDIP or 44-pin PLCC/QFP package.

 

Description : 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with EThernet, USB 2.0 Host/device/OTG, CAN

General description
The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of The LPC1759/58/56/54/52/51 includes up to 512 kB of flash memory, up to 64 kB of data memory, EThernet MAC, USB device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 2 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 6 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 52 general purpose I/O pins.

Features
■ ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit (MPU) supporting eight regions is included.
■ ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
■ Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.
■ In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
■ On-chip SRAM includes:
   ♦ Up to 32 kB of SRAM on The CPU with local code/data bus for high-performance CPU access.
   ♦ Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
      These SRAM blocks may be used for EThernet (LPC1758 only), USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
■ Eight channel General Purpose DMA controller (GPDMA) on The AHB multilayer matrix that can be used with The SSP, I2S-bus, UART, The Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.
■ Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
   AHB masters include The CPU, General Purpose DMA controller, EThernet MAC (LPC1758 only), and The USB interface. This interconnect provides communication with no arbitration delays.
■ Split APB bus allows high throughput with few stalls between The CPU and DMA.
■ Serial interfaces:
   ♦ On The LPC1758 only, EThernet MAC with RMII interface and dedicated DMA controller.
   ♦ USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB device controller only.
   ♦ Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.
   ♦ CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.
   ♦ SPI controller with synchronous, serial, full duplex communication and programmable data length.
   ♦ Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with The GPDMA controller.
   ♦ Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode.
   ♦ On The LPC1759/58/56 only, I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with The GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output.
■ OTher peripherals:
   ♦ 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through The AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by The General Purpose DMA Controller.
   ♦ 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with The GPDMA controller.
   ♦ On The LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.
   ♦ Four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.
   ♦ One motor control PWM with support for three-phase motor control.
   ♦ Quadrature encoder interface that can monitor one external quadrature encoder.
   ♦ One standard PWM/timer block with external count input.
   ♦ Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.
   ♦ Watchdog Timer (WDT). The WDT can be clocked from The internal RC oscillator, The RTC oscillator, or The APB clock.
   ♦ ARM Cortex-M3 system tick timer, including an external clock input option.
   ♦ Repetitive Interrupt Timer (RIT) provides programmable and repeating timed interrupts.
   ♦ Each peripheral has its own clock divider for furTher power savings.
■ Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.
■ Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.
■ Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.
■ Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
■ Single 3.3 V power supply (2.4 V to 3.6 V).
■ One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.
■ Non-maskable Interrupt (NMI) input.
The Wakeup Interrupt Controller (WIC) allows The CPU to automatically wake up from any priority interrupt that can occur while The clocks are stopped in Deep sleep, Power-down, and Deep power-down modes.
■ Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, EThernet wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).
■ Brownout detect with separate threshold for interrupt and forced reset.
■ Power-On Reset (POR).
■ Crystal oscillator with an operating range of 1 MHz to 25 MHz.
■ 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.
■ PLL allows CPU operation up to The maximum CPU rate without The need for a high-frequency crystal. May be run from The main oscillator, The internal RC oscillator, or The RTC oscillator.
■ USB PLL for added flexibility.
■ Code Read Protection (CRP) with different security levels.
■ Unique device serial number for identification purposes.
■ Available as 80-pin LQFP package (12 mm × 12 mm × 1.4 mm).

Applications
■ eMetering
■ Lighting
■ Industrial networking
■ Alarm systems
■ White goods
■ Motor control

 

Myson
Myson Century Inc
Description : 8051 embedded Monitor Controller Flash Type with ISP

GENERAL DESCRIPTIONS
The MTV212M64i micro-controller is an 8051 CPU core embedded device especially tailored to Monitor applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs, VESA DDC interface, 4-channel A/D converter and a 64K-byte internal program Flash-ROM.

FEATURES
· 8051 core, 12MHz operating frequency.
· 1024-byte RAM; 64K-byte program Flash-ROM support In System Programming(ISP).
· Maximum 14 channels of 5V open-drain PWM DAC.
· Maximum 32 bi-directional I/O pins.
· SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment and programmable clamp pulse output.
· Built-in self-test pattern generator with four free-running timings.
· Built-in low power reset circuit.
· Compliant with VESA DDC1/2B/2Bi/2B+ standard.
· Dual slave IIC addresses.
· Single master IIC interface for internal device communication.
· 4-channel 6-bit ADC.
· Watchdog timer with programmable intervals.
· 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

 

Myson
Myson Century Inc
Description : 8051 embedded USB/PS2 Keyboard/Mouse Controller

GENERAL DESCRIPTIONS
The MTP805 micro-controller is an 8051 CPU core embedded device specially tailored to USB/PS2 Keyboard/Mouse applications. It includes an 8051 CPU core, 256-byte SRAM, Low Speed USB Interface and an 8K-byte internal program Flash-ROM.

FEATURES
8051 core, 6MHz operating frequency.
• 256-byte RAM, 8K-byte program Flash-ROM.
• Compliant with Low Speed USB Spec.1.1 including 3 Endpoints: one is Control endpoint (8-byte IN & 8-byte OUT FIFOs), The oTher two are Interrupt endpoints (8-byte IN FIFOs).
• Built-in 3.3V regulator for USB Interface.
• Suspend / Resume operation.
• Idle and Power down mode wake-up by interrupt.
• 8 dedicated Key scan input pins and 18/19 Key scan output pins.
• Built-in low power reset circuit and Watchdog timer.
• PS2 compatible mouse interface.
• PS2 compatible keyboard interface share with USB interface.
CPU clock can be double by S/W setting.
• 40-pin DIP, 42-pin SDIP or 44-pin PLCC package.

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