Synchronous 4Bit Binary Counters (Synchronous clear)
BCD DECADE Counters/4Bit Binary Counters
The LS160A/161A/162A/163A are highspeed 4Bit Synchronous Counters. They are edgetriggered, Synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (Binary.)
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• EdgeTriggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
BCD DECADE Counters/4Bit Binary Counters
The LS160A/161A/162A/163A are highspeed 4Bit Synchronous Counters. They are edgetriggered, Synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (Binary.)
The LS160A and LS161A have an aSynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge.
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• EdgeTriggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
Dual 4Bit Binary Counters
This circuit contains eight masterslave flipflops and additional gating to implement two individual fourbit Counters.
The HD74LS393 comprises two independent fourbit Binary Counters each having a clear and a clock input.
Nbit Binary counter can be implemented with each package providing the capability of divideby258.
Synchronous 4 Bit Counters; Binary, Direct Reset
This Synchronous, presettable counter features an internal carry lookahead for application in highspeed counting designs. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change conicident with each other when so instructed by the countenable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are normally associated with aSynchronous (ripple clock) Counters. A buffered clock input triggers the four flipflops on the rising (positivegoing) edge of the clock input wave form.
• Internal LookAhead for Fast Counting
• Carry Output for nBit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• DiodeClamped Inputs
Synchronous 4 Bit Counters; Binary, Direct Reset
This Synchronous, presettable counter features an internal carry lookahead for application in highspeed counting designs. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change conicident with each other when so instructed by the countenable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are normally associated with aSynchronous (ripple clock) Counters. A buffered clock input triggers the four flipflops on the rising (positivegoing) edge of the clock input wave form.
• Internal LookAhead for Fast Counting
• Carry Output for nBit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• DiodeClamped Inputs
General Description
These Synchronous, presettable Counters feature an internal carry lookahead for application in highspeed counting designs. They are 4Bit Binary Counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with aSynchronous (ripple clock) Counters. A buffered clock input triggers the four flipflops on the rising (positivegoing) edge of the clock input waveform.
Features
■ Synchronously programmable
■ Internal lookahead for fast counting
■ Carry output for nbit cascading
■ Synchronous counting
■ Load control line
■ Diodeclamped inputs
Synchronous 4 Bit Counters; Binary, Direct Reset
This Synchronous, presettable counter features an internal carry lookahead for application in highspeed counting designs. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change conicident with each other when so instructed by the countenable inputs and internal gating.
• Internal LookAhead for Fast Counting
• Carry Output for nBit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• DiodeClamped Inputs
General Description
These Synchronous, presettable Counters feature an internal carry lookahead for application in highspeed counting designs. The DM74LS161A and DM74LS163A are 4Bit Binary Counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation eliminates the output counting
spikes which are normally associated with aSynchronous (ripple clock) Counters. A buffered clock input triggers the four flipflops on the rising (positivegoing) edge of the clock input waveform.
Features
■Synchronously programmable
■Internal lookahead for fast counting
■Carry output for nbit cascading
■Synchronous counting
■Load control line
■Diodeclamped inputs
■Typical propagation time, clock to Q output 14 ns
■Typical clock frequency 32 MHz
■Typical power dissipation 93 mW
PRESETTABLE BCD/DECADE UP/DOWN Counters
PRESETTABLE 4Bit Binary UP/DOWN Counters
The SN54/74LS190 is a Synchronous UP/DOWN BCD Decade (8421) Counter and the SN54/74LS191 is a Synchronous UP/DOWN Modulo16 Binary Counter. State changes of the Counters are Synchronous with the LOWtoHIGH transition of the Clock Pulse input.
An aSynchronous Parallel Load (PL) input overrides counting and loads the data present on the Pn inputs into the flipflops, which makes it possible to use the circuits as programmable Counters. A Count Enable (CE) input serves as the carry /borrow input in multistage Counters. An Up/Down Count Control (U/D) input determines whether a circuit counts up or down. A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indication and make possible a variety of methods for generating carry/borrow signals in multistage counter applications.
• Low Power . . . 90 mW Typical Dissipation
• High Speed . . . 25 MHz Typical Count Frequency
• Synchronous Counting
• ASynchronous Parallel Load
• Individual Preset Inputs
• Count Enable and Up/Down Control Inputs
• Cascadable
• Input Clamp Diodes Limit High Speed Termination Effects
