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Part Name(s) : 74HCT377 74HC377 ETC1
Unspecified
Description : OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER

OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER

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Part Name(s) : 74AC11378 74ACT11378 74AC11378D 74ACT11378D 74AC11378N 74ACT11378N Philips
Philips Electronics
Description : Hex D-TYPE FLIP-FLOP with enable, positive edge TRIGGER

Hex D-TYPE FLIP-FLOP with enable, positive edge TRIGGER

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Part Name(s) : SN54LS74AJ SN74LS74A SN74LS74AD SN74LS74AN SN54LS74A Motorola
Motorola => Freescale
Description : DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS74A dual edge-TRIGGERed FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has individual clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock TRIGGERing occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

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Part Name(s) : SN74LS74A SN74LS74AN SN74LS74AD ONSEMI
ON Semiconductor
Description : Dual D−Type Positive Edge−TRIGGERed Flip−Flop

The SN74LS74A dual edge-TRIGGERed FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has individual clear and set inputs, and also complementary Q and Q outputs.

Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock TRIGGERing occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
   

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Part Name(s) : 74F50728 I74F50728D I74F50728N N74F50728D N74F50728N Philips
Philips Electronics
Description : Synchronizing cascaded dual positive edge-TRIGGERed D-TYPE FLIP-FLOP

DESCRIPTION
The 74F50728 is a cascaded dual positive edge–TRIGGERed D–type featuring individual data, clock, set and reset inputs; also true and complementary outputs.

FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• See 74F5074 for synchronizing dual D-TYPE FLIP-FLOP
• See 74F50109 for synchronizing dual J–K positive edge-TRIGGERed FLIP-FLOP
• See 74F50729 for synchronizing dual dual D-TYPE FLIP-FLOP with edge-TRIGGERed set and reset
• Industrial temperature range available (–40°C to +85°C)

 

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Part Name(s) : 74AHC1G79 74AHC1G79GW 74AHCT1G79 74AHCT1G79GW Philips
Philips Electronics
Description : SINGLE D-TYPE FLIP-FLOP; POSITIVE-EDGE TRIGGER

DESCRIPTION
The 74AHC1G/AHCT1G79 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G79 provides a SINGLE POSITIVE-EDGE TRIGGERed D-TYPE FLIP-FLOP. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

FEATURES
• Symmetrical output impedance
• High noise immunity
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V;
MM EIA/JESD22-A115-A exceeds 200 V
• Low power dissipation
• Balanced propagation delays
• Very small 5 pin package
• Output capability: standard.

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Part Name(s) : 74HC 74HC109 74HCT109 74HC/HCT109 Philips
Philips Electronics
Description : Dual JK FLIP-FLOP with set and reset; POSITIVE-EDGE TRIGGER

GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT109 are dual POSITIVE-EDGE TRIGGERed, JK FLIP-FLOPs with individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
The J and K inputs control the state changes of the FLIP-FLOPs as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The JK design allows operation as a D-TYPE FLIP-FLOP by tying the J and K inputs together.
Schmitt-TRIGGER action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• J, K inputs for easy D-TYPE FLIP-FLOP
• Toggle FLIP-FLOP or “do nothing” mode
• Output capability: standard
• ICC category: FLIP-FLOPs

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Part Name(s) : 74AHC377 74AHC377D 74AHC377PW 74AHCT377 74AHCT377D 74AHCT377PW Philips
Philips Electronics
Description : Octal D-TYPE FLIP-FLOP with data enable; POSITIVE-EDGE TRIGGER

DESCRIPTION
The 74AHC/AHCT377 D-TYPE FLIP-FLOPs are high-speed silicon-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-TRIGGERed, D-TYPE FLIP-FLOPs with individual D inputs and Q outputs. A common clock (CP) input loads all FLIP-FLOPs simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the FLIP-FLOP.
The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.

FEATURES
• ESD protection:
   HBM EIA/JESD22-A114-A exceeds 2000 V
   MM EIA/JESD22-A115-A exceeds 200 V
   CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-TRIGGER actions
• Inputs accept voltages higher than VCC
• Ideal for addressable register applications
• Data enable for address and data synchronization
• Eight POSITIVE-EDGE TRIGGERed D-TYPE FLIP-FLOPs
• See “273” for master reset version
• See “373” for transparent latch version
• See “374” for 3-state version
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and from −40 to +125 °C.

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Part Name(s) : MC54F74 MC54F74J MC74F74 MC74F74D MC74F74J MC74F74N Motorola
Motorola => Freescale
Description : Dual D-TYPE positive edge-TRIGGERed FLIP-FLOP

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST SCHOTTKY TTL

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Part Name(s) : 74LVC1G80 74LVC1G80GF 74LVC1G80GM 74LVC1G80GV 74LVC1G80GW NXP
NXP Semiconductors.
Description : SINGLE D-TYPE FLIP-FLOP; POSITIVE-EDGE TRIGGER

General description
The 74LVC1G80 provides a SINGLE POSITIVE-EDGE TRIGGERed D-TYPE FLIP-FLOP.
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Features
■ Wide supply voltage range from 1.65 V to 5.5 V
■ High noise immunity
■ Complies with JEDEC standard:
   ◆ JESD8-7 (1.65 V to 1.95 V)
   ◆ JESD8-5 (2.3 V to 2.7 V)
   ◆ JESD8B/JESD36 (2.7 V to 3.6 V)
■ ±24 mA output drive (VCC = 3.0 V)
■ CMOS low power consumption
■ Latch-up performance exceeds 250 mA
■ Direct interface with TTL levels
■ Inputs accept voltages up to 5 V
■ Multiple package options
■ ESD protection:
   ◆ HBM JESD22-A114E exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +125 °C

 

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