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Part Name(s) : XRT91L32 XRT91L32IQ-F Exar
Exar Corporation
Description : OR="FF003B">STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER View

GENERAL DESCRIPTION
The XRT91L32 is a fully integrated SONET/SDH TRANSCEIVER fOR SONET/SDH 622.08 Mbps STS-12/ STM-4 OR 155.52 Mbps STS-3/STM-1 applications. The TRANSCEIVER includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled OscillatOR (VCO) to the incoming serial data stream.

FEATURES
• Targeted fOR SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
• Selectable full duplex operation between OR="FF003B">STS-12/STM-4 standard rate of 622.08 Mbps OR STS-3/STM-1 155.52 Mbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
• Ability to disable and bypass onchip CDR fOR external based received reference clock recovery thru Differential LVPECL input pins XRXCLKIP/N
• 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in OR="FF003B">STS-12/STM-4 OR 19.44 Mbps in STS-3/STM-1 mode of operation
• Uses Differential LVPECL OR Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz OR 77.76 MHz fOR both STS-12/STM-1 OR STS-3/STM-1 operations
• Optional use of 77.76 MHz Single-Ended LVTTL input fOR independent CDR reference clock operation
• Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus
• Diagnostics features include LOS monitORing and automatic received data mute upon LOS
• Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
• Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the TRANSCEIVER transmit timing.
• Meets TelcORdia, ANSI, BellcORe TR-NWT-000253 and GR-253-CORE, and G.783 ITU-T jitter requirements
• Operates at 3.3V with 3.3V I/O
• Less than 660mW in STS-3/STM-1 mode OR 800mW in OR="FF003B">STS-12/STM-4 mode Typical Power Dissipation
• Package: 10 x 10 x 2.0 mm 100-pin QFP

APPLICATIONS
SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and Switch/Routers
• DSLAMS
SONET/SDH Test Equipment
• DWDM Termination Equipment

Part Name(s) : CS4805 S4805CBI S4805CBI11 AMCC
Applied Micro Circuits Corporation
Description : SONET/SDH STS-48/STM-16 Framer/Pointer ProcessOR View

SONET/SDH STS-48/STM-16 Framer/Pointer ProcessOR

SONET/SDH Mux/Demux, TranspORt Overhead Terminating TRANSCEIVER and Pointer ProcessORs fOR STS-48/STM-16 and up to 4 x OR="FF003B">STS-12/STM-4 OR 16 x STS-3/STM-1s.
• Serial OR="FF003B">STS-12/STM-4 and STS-3/STM-1 interfaces.
• Provisionable as SONET OR SDH on a per line basis.
• Provisionable as SOH/LOH pass-through OR termination/regeneration device.
• Built-in 192x48 cross-connects fOR STS-1 level cross-connection OR add/drop, in both Mux and Demux directions.
• Compliant with BellcORe GR-253, ITU G.707, and ANSI T1.105-1995 standards.

Part Name(s) : XRT91L30 XRT91L306 XRT91L30IQ XRT91L30IQ-F Exar
Exar Corporation
Description : OR="FF003B">STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER View

GENERAL DESCRIPTION
The XRT91L30 is a fully integrated SONET/SDH TRANSCEIVER fOR SONET/SDH 622.08 Mbps STS-12/ STM-4 OR 155.52 Mbps STS-3/STM-1 applications. The TRANSCEIVER includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase Locked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled OscillatOR (VCO) to the incoming serial data stream. The internal CDR unit can be disabled

FEATURES
• Targeted fOR SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
• Selectable full duplex operation between OR="FF003B">STS-12/STM-4 standard rate of 622.08 Mbps OR STS-3/STM-1 155.52 Mbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
• Ability to disable and bypass onchip CDR fOR external based received reference clock recovery thru Differential LVPECL input pins XRXCLKIP/N
• 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in OR="FF003B">STS-12/STM-4 OR 19.44 Mbps in STS-3/STM-1 mode of operation
• Uses Differential LVPECL OR Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz OR 77.76 MHz fOR both STS-12/STM-1 OR STS-3/STM-1 operations
• Optional use of 77.76 MHz Single-Ended LVTTL input fOR independent CDR reference clock operation
• Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus
• Diagnostics features include LOS monitORing and automatic received data mute upon LOS
• Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
• Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the TRANSCEIVER transmit timing.
• Meets TelcORdia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, BellcORe TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET
Jitter specifications.
• Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B LVTTL and LVCMOS standard.
• Operates at 3.3V CORe with 3.3V I/O
• Less than 660mW in STS-3/STM-1 mode OR 800mW in OR="FF003B">STS-12/STM-4 mode Typical Power Dissipation
• Package: 10 x 10 x 2.0 mm 64-pin QFP

APPLICATIONS
SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS
SONET/SDH Test Equipment
• DWDM Termination Equipment

Part Name(s) : XRT91L31 XRT91L31IQ XRT91L31 XRT91L31IQ XRT91L31IQ-F Exar
Exar Corporation
Description : OR="FF003B">STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER View

GENERAL DESCRIPTION
The XRT91L31 is a fully integrated SONET/SDH TRANSCEIVER fOR SONET/SDH 622.08 Mbps OR="FF003B">STS-12/STM-4 OR 155.52 Mbps STS-3/STM-1 applications. The TRANSCEIVER includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled OscillatOR (VCO) to the incoming serial data stream.

FEATURES
• Targeted fOR SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
• Selectable full duplex operation between OR="FF003B">STS-12/STM-4 standard rate of 622.08 Mbps OR STS-3/STM-1 155.52 Mbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
• Ability to disable and bypass onchip CDR fOR external based received reference clock recovery thru Differential LVPECL input pins XRXCLKIP/N
• 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in OR="FF003B">STS-12/STM-4 OR 19.44 Mbps in STS-3/STM-1 mode of operation
• Uses Differential LVPECL OR Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz OR 77.76 MHz fOR both STS-12/STM-1 OR STS-3/STM-1 operations
• Optional use of 77.76 MHz Single-Ended LVTTL input fOR independent CDR reference clock operation
• Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus
• Diagnostics features include LOS monitORing and automatic received data mute upon LOS
• Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
• Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the TRANSCEIVER transmit timing.
• Meets TelcORdia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, BellcORe TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET Jitter specifications.
• Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B LVTTL and LVCMOS standard.
• Operates at 3.3V with 3.3V I/O
• Less than 660mW in STS-3/STM-1 mode OR 800mW in OR="FF003B">STS-12/STM-4 mode Typical Power Dissipation
• Package: 10 x 10 x 2.0 mm 64-pin QFP

APPLICATIONS
SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and Switch/Routers
• DSLAMS
SONET/SDH Test Equipment
• DWDM Termination Equipment


Part Name(s) : XRT91L34 XRT91L34IV XRT91L34IV-F Exar
Exar Corporation
Description : QUAD CHANNEL MULTIRATE STS-12/3/1 AND STM-4/1/0 SONET/SDH CDR View

GENERAL DESCRIPTION
The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device fOR SONET/SDH 622.08 Mbps OR="FF003B">STS-12/STM-4 OR 155.52 Mbps STS-3/STM-1 OR 51.84 Mbps STS-1/STM-0 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled OscillatOR (VCO) to the incoming serial data stream. The device internally monitORs Loss of Lock (LOL) conditions and automatically mutes recovered data upon Loss of Signal (LOS) conditions.

FEATURES
• Quad Channel CDR targeted fOR SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications
• Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, OR 51.84 Mbps.
• Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions
• Optional flexibility to configure fOR LVDS OR Differential LVPECL High Speed I/O Interface
• Internal 100Ω termination fOR the high speed LVDS/Differential LVPECL inputs included
• Utilizes reference clock frequency of either 19.44 MHz OR 77.76 MHz
• Host mode serial microprocessOR interface simplifies monitOR and control, including LOS monitORing
• Diagnostics features include LOS monitORing in Host Mode and automatic recovered data mute upon LOS
• Loss of Lock Detect output fOR each channel
• Permits mixed data rate configuration of the four channels
• Independent power down control of unused channels fOR lower power operation
• Meets TelcORdia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.
• Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and JESD 8-B LVTTL and LVCMOS standard.
• Operates with dual power supply of 1.8V cORe and 3.3V IO supply
• 90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation
• Package: 14 x 14 x 1.4 mm 128-pin LQFP
• RoHS Compliant Lead-Free package availability
• ESD greater than 2kV on all pins

APPLICATIONS
SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and Switch/Routers
• DSLAMS
SONET/SDH Test Equipment
• DWDM Termination Equipment

 

Part Name(s) : VSC9186 Vitesse
Vitesse Semiconductor
Description : Killington - Quad STS-48/STM-16 and STS-192/STM-64 Line Interface View

Description
The VSC9186 is a bidirectional quad STS-48/STM-16 OR OC-192/STM-64 framer and pointer processOR. In addition to full path overhead monitORing, section and line termination are available on line inputs and outputs. A bidirectional protection interface allows both line and tributary traffic to be looped back simultaneously through a companion device. The UPSR is implemented entirely in hardware driven by the STE/LTE logic, pointer interpreter and path overhead monitOR.

Part Name(s) : TMXF84622 Agere
Agere -> LSI Corporation
Description : 155 Mbits/s/622 Mbits/s Interface SONET/SDH x84/x63 Ultramapper View

The SONET/SDH Ultramapper
Overview
The SONET/SDH Ultramapper device integrates the SONET/SDH line, path, and tributary termination functions with M13/E13 multiplex functions and the primary rate framing function. It is designed to drive either an OC-12/STM-4 OR OC-3/STM-1 optical signal directly OR to allow fOR modular growth in terminal OR add/drop applications.

The Ultramapper provides a versatile interface fOR all OR="FF003B">STS-12/STM-4, STS-3/STM-1, and STS-1 termination applications in point-to-point scenarios and fOR ring applications. This chip can be used in tributary shelf applications fOR up to 84 T1 OR J1 OR 63 E1 line cards, providing all possible mappings into SONET/SDH, because of the flexibility of the mappings, software upgrades from M13/E13 mapped connections to VT/TU mapped connections are possible. This device can also be used fOR DS3/E3/DS2 applications.

A single Ultramapper is capable of processing the aggregate bandwidth of one STS-3/STM-1 to 84/63 DS1/E1s. Further, a single Ultramapper can process the aggregate bandwidth of two STS-3/STM-1s, terminated as an OR="FF003B">STS-12/STM-4, to six DS3/E3s. Additionally, a single Ultramapper can function as an STS-12/STS-3/STM-4/STM-1 add-drop MUX by terminating up to three STS-1/STM-0 channels OR one AU-4 channel and using the internal pointer processORs to fORward any nonterminated channels. By communicating to three other mate devices via the serial STS-3/STM-1 link interface, it is capable of terminating a full OR="FF003B">STS-12/STM-4 signal.

 

Part Name(s) : CS4804 S4804CBI AMCC
Applied Micro Circuits Corporation
Description : OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER View

The S4804 is a highly-integrated VLSI device that provides full-duplex mapping of packets OR ATM cells to SONET/SDH payloads. It provides suppORt fOR both uni-directional and bi-directional rings.

Features
• Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM- 4, OR 16 STS-3/STM-1 line interfaces.
• STS-48/STM-16 data stream suppORts a single STS-48c/AU-4-16c, OR any valid combination of STS-12c/AU-4-4c and/OR STS-3c/AU-4 SONET/SDH payloads.
• Each OR="FF003B">STS-12/STM-4 data stream suppORts a single STS- 12c/AU-4-4c OR 4 STS-3c/AU-4 SONET/SDH payloads.
• Each STS-3/STM-1 data stream suppORts a single STS-3c/AU-4 SONET/SDH payload.
• SuppORts mixed STS-3 / STS-12 line rates
• Provides full-duplex mapping of ATM cells OR packets in each payload tributary.
• SuppORts termination of mixed ATM and POS tributaries.
• Terminates/generates SONET/SDH section, line, and path layers with transpORt/section E1, E2, F1, and DCC overhead interfaces in both transmit and receive directions.
• APS pORt to suppORt protection-switching configurations between two RHINE devices.
• 16-bit, bus interface at 155 MHz fOR STS-48/STM-16 mode, OR serial interfaces operating at 622/155 MHz fOR STS-12/3 (STM-4/1) modes on the line side.
• 32-bit, parallel interface (FlexBus-3TM) operating at 100 MHz on the system side.
• .25 micron, 2.5V cORe, and 3.3V tolerant I/O.
• Packaged in a 624 Pin CBGA.

Applications
• ATM switches
• Packet over SONET Routers and Switches
SONET/SDH Add Drop Multiplexers, Terminal Multiplexers, and Digital Cross Connects
• Test equipment

Part Name(s) : XRT91L80 XRT91L80IB XRT91L80 XRT91L80IB Exar
Exar Corporation
Description : 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER View

GENERAL DESCRIPTION
The XRT91L80 is a fully integrated SONET/SDH TRANSCEIVER fOR SONET OC-48 allowing the use of FORward ErrOR CORrection (FEC) capability.

FEATURES
• 2.488 / 2.666 Gbps TRANSCEIVER
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, limiting amplifier and clock data recovery (CDR) functions
• Host mode serial microprocessOR interface simplifies monitOR and control
• Separate reference and VCXO input pORts suppORt multiple de-jittering modes
• On-chip phase detectOR and charge pump fOR external VCXO based de-jittering PLL
• Targeted fOR SONET OC-48/SDH STM-16 Applications
• Selectable full duplex operation between standard rate of 2.488 Gbps OR FORward ErrOR CORrection rate of 2.666 Gbps
• 4-bit LVDS data paths at 622/666 MHz compliant with OIF SFI-4 Implimentation Agreement
• Internal FIFO decouples transmit input and output clocks
• Tx CMU and Rx CDR lock detect
• Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
• Diagnostics features include various lock detect functions
• Meets TelcORdia, ANSI and ITU-T jitter requirements
• Operates at 1.8V with 3.3V I/O
• 420mW Typical Power Dissipation
• Package: 12 x 12 mm 196-pin STBGA
• IEEE 1149.1 Compatable JTAG pORt

APPLICATIONS
SONET/SDH-based Transmission Systems
• Add/Drop Multiplexers
• Cross Connect Equipment
• ATM and Multi-Service Switches, Routers and Switch/Routers
• DSLAMS
SONET/SDH Test Equipment
• DWDM Termination Equipment

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