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Part Name(s) : TC4021 TC4021B TC4021BF TC4021BFN TC4021BP Toshiba
Toshiba
Description : 8-Stage Static Shift Register (asynchronous parallel input or synchronous SERIAL input/SERIAL output) View

TC4021B is 8 stage parallel in/SERIAL out shift register, which can be used also for SERIAL in/SERIAL out operations. In the case of parallel operation, the data of PARALLEL IN is input to each F/F asynchronously with CLOCK and the output is obtained. In the case of SERIAL operations, each F/F is triggered by rising edge of CLOCK. (asynchronous parallel or synchronous SERIAL input) Switching of PARALLEL operation and SERIAL operation is achieved by P/ S CONTROL input. When P/ S CONTROL input is “H”, PARALLEL operation is designated and when it is “L”, SERIAL operation is designated.

Part Name(s) : LH0084 LH0084A LH0084AH LH0084B LH0084H LH0085 LH0085A LH0085AH LH0085B LH0085H LH0086 LH0086A LH0086AH LH0086B LH0086H LH0087 LH0087A LH0087AH LH0087B LH0087H LH0087M LH0087U LH0087AM LH0087AU LH0087BU ETC
Unspecified
Description : Z80 SIO SERIAL INPUT/OUTPUT CONTROLLER View

[Sharp]

Z80 SIO SERIAL INPUT/OUTPUT CONTROLLER

Part Name(s) : MC74HC589A MC74HC589AN MC74HC589ANG MC74HC589AD MC74HC589ADG MC74HC589ADR2 MC74HC589ADR2G MC74HC589ADTR2 MC74HC589AFEL MC74HC589AFELG ONSEMI
ON Semiconductor
Description : 8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with 3-State Output View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with 3-State Output
High−Performance Silicon−Gate CMOS

The MC74HC589A device consists of an 8−bit storage latch which feeds parallel data to an 8−bit shift register. Data can also be loaded SERIALly (see the Function Table). The shift register output, QH, is a 3−state output, allowing this device to be used in bus−oriented systems.
The HC589A directly interfaces with the SPI SERIAL data port on CMOS MPUs and MCUs.

Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 μA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates
• Pb−Free Packages are Available*

Part Name(s) : MC54/74HC589 MC54HC589 MC54HC589J MC74HC589 MC74HC589N MC74HC589D Motorola
Motorola => Freescale
Description : 8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with 3-State Output View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with 3-State Output
High–Performance Silicon–Gate CMOS

The MC54/74HC589 is similar in function to the HC597, which is not a 3–state device. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8–bit storage latch which feeds parallel data to an 8–bit shift register. Data can also be loaded SERIALly (see Function Table).
The shift register output, QH, is a three–state output, allowing this device to be used in bus–oriented systems.
The HC589 directly interfaces with the Motorola SPI SERIAL data port on CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates


Part Name(s) : IN74HC597A IN74HC597AD IN74HC597AN IKSEMICON
IK Semicon Co., Ltd
Description : 8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with Input Latch View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register with Input Latch
High-Performance Silicon-Gate CMOS

The IN74HC597A is identical in pinout to the LS/ALS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit input latch which feeds parallel data to an  8-bit  shift  register.  Data  can  also  be  loaded  SERIALly  (see  Function Table).

•  Outputs Directly Interface to CMOS, NMOS, and TTL
•  Operating Voltage Range: 2.0 to 6.0 V
•  Low Input Current: 1.0 µA
•  High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : IN74HC166 IN74HC166D IN74HC166N INTE-ElectronicGRAL
Integral Corp.
Description : 8-Bit SERIAL or Parallel-Input/ SERIAL-Output Shift Register View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register
High-Performance Silicon-Gate CMOS

The IN74HC166 is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or SERIAL-in, SERIAL-out shift register with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or SERIAL-in mode. When high, this input enables the SERIAL data input and couples the eight flip-flops for SERIAL shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. SERIAL data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : IN74HC166A IN74HC166AN IN74HC166AD IKSEMICON
IK Semicon Co., Ltd
Description : 8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register
High-Performance Silicon-Gate CMOS

The IN74HC166A is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or SERIAL-in, SERIAL-out shift register with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or SERIAL-in mode. When high, this input enables the SERIAL data input and couples the eight flip-flops for SERIAL shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. SERIAL data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : IN74HC166 IN74HC166D IN74HC166N Integral
Integral Corp.
Description : 8-Bit SERIAL or Parallel-Input/ SERIAL-Output Shift Register View

8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register
High-Performance Silicon-Gate CMOS

The IN74HC166 is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or SERIAL-in, SERIAL-out shift register with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or SERIAL-in mode. When high, this input enables the SERIAL data input and couples the eight flip-flops for SERIAL shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. SERIAL data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices

Part Name(s) : SL74HC166D SL74HC166N SL74HC166 SLS
System Logic Semiconductor
Description : 8-Bit SERIAL or Parallel-Input/SERIAL-Output Shift Register View

8-Bit SERIAL or Parallel-Input/ SERIAL-Output Shift Register
High-Performance Silicon-Gate CMOS

The SL74HC166 is identical in pinout to the LS/ALS166. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device is a parallel-in or SERIAL-in, SERIAL-out shift register with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or SERIAL-in mode. When high, this input enables the SERIAL data input and couples the eight flip-flops for SERIAL shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. SERIAL data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, andsets all flip-flop to zero.

● Outputs Directly Interface to CMOS, NMOS, and TTL
● Operating Voltage Range: 2.0 to 6.0 V
● Low Input Current: 1.0 mA
● High Noise Immunity Characteristic of CMOS Devices

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