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Part Name(s) : 74AC175CW 74ACT175CW 74ACT175PC Fairchild
Fairchild Semiconductor
Description : Quad D-Type Flip-Flop View

The 74AC175/74ACT175 (AC/ACT175) is a high-speed Quad D-type Flip-Flop.

The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to HIGH clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D-type inputs, when LOW.

Part Name(s) : DM74S174 DM74S174N DM74S175 DM74S175N Fairchild
Fairchild Semiconductor
Description : Hex/Quad D Flip-Flop with Clear View

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type Flip-Flop logic. All have a direct clear input, and the Quad (DM74S175) versions feature comple mentary outputs from each Flip-Flop.

Features
■DM74S174 contain six Flip-Flops with single-rail outputs.
■DM74S175 contain four Flip-Flops with double-rail outputs.
■Buffered clock and direct clear inputs
■Individual data input to each Flip-Flop
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical power dissipation per Flip-Flop 75mW

Part Name(s) : 74AC175 74ACT175 ON-Semiconductor
ON Semiconductor
Description : Quad D Flip-Flop WITH MASTER RESET View

Quad D Flip-Flop With Master Reset

The MC74AC/ACT175 is a high-speed Quad D Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all Flip-Flops, when MR is low.
The MC74AC/ACT175 consists of four edge-triggered D Flip-Flops with individual D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common to all Flip-Flops. Each D input’s state is transferred to the corresponding Flip-Flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and Master Reset are common to all storage elements.

• Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs

Part Name(s) : MC54F175 MC54F175J MC74F175 MC74F175D MC74F175N Motorola
Motorola => Freescale
Description : Quad D Flip-Flop FAST™ SCHOTTKY TTL View

Quad D Flip-Flop
The  MC54/74F175  is  a  high-speed  Quad  D  Flip-Flop.  The  device  is  useful  for general Flip-Flop  requirements  where both true  and complementary outputs are required and clock and clear inputs are common to all Flip-Flops. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input  resets  all Flip-Flops,  independent  of the  Clock or D inputs  when LOW.

·  Four Edge-triggered D-type Inputs
·  Buffered Positive Edge-triggered Common Clock
·  Buffered Asynchronous Common Reset
·  True and Complementary Outputs
·  ESD  > 4000 Volts


Part Name(s) : HD74AC175 HD74AC175AFPEL HD74AC175ARPEL HD74AC175TELL Renesas
Renesas Electronics
Description : Quad D-Type Flip-Flop View

Description
The HD74AC175 is a high-speed Quad D Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D inputs, when Low.

Features
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA

Part Name(s) : 74F175 74F175PC 74F175SC 74F175SCX 74F175SJ 74F175SJX Fairchild
Fairchild Semiconductor
Description : Quad D-Type Flip-Flop View

General Description
The 74F175 is a high-speed Quad D-type Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D inputs, LOW.

Features
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ True and complement output

Part Name(s) : MC74AC175 MC74AC175D MC74AC175N MC74ACT175 MC74ACT175D MC74ACT175N Motorola
Motorola => Freescale
Description : Quad D Flip−Flop With Master Reset View

The MC74AC/ACT175 is a high-speed Quad D Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all Flip-Flops, when MR is low.

• Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs

Part Name(s) : DV74AC175 DV74ACT175 DV74AC175N DV74ACT175N DV74AC175D DV74ACT175D AVG
AVG Semiconductors=>HITEK
Description : Quad D Flip-Flop with Master Reset View

Quad D Flip-Flop with Master Reset

Part Name(s) : MC14175BCP MC14175BD MC14175BDR2 MC14175BFEL ON-Semiconductor
ON Semiconductor
Description : Quad Type D Flip−Flop View

Quad Type D Flip−Flop
The MC14175B Quad type D flip−flop is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each of the four flip−flops is positive−edge triggered by a common clock input (C). An active−low reset input (R) asynchronously resets all flip−flops.

Features
•Complementary Outputs
•Static Operation
•All Inputs and Outputs Buffered
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Output Compatible with Two Low−Power TTL Loads or One Low−Power Schottky TTL Load
•Functional Equivalent to TTL 74175
•Pb−Free Packages are Available*

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