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ON Semiconductor
Description : Quad 2−Input Multiplexer (Inverting)

Quad 2−Input Multiplexer (Inverting)

The MC10H159 is a Quad 2–input Multiplexer with enable. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay and no increase in power–supply current.

• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 218 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible

Motorola
Motorola => Freescale
Description : Quad 2−Input Multiplexer (Inverting)

Quad 2−Input Multiplexer (Inverting)

The MC10H159 is a Quad 2–input Multiplexer with enable. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay and no increase in power–supply current.

• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 218 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible

Motorola
Motorola => Freescale
Description : Quad 2-INPUT Multiplexer WITH 3-STATE OUTPUTS

Quad 2-INPUT Multiplexer WITH 3-STATE OUTPUTS

The MC74F258A is a Quad 2-input Multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common Data Select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Multiplexer Expansion by Tying Outputs Together
Inverting 3-State Outputs
• AC Enhanced Version of the F258

Description : Quad 2-Input Multiplexer Non-Inverting

Description
The CD54AC157/3A is a Quad 2-input Multiplexer that utilizes the Harris Advanced CMOS Logic technology.
The CD54AC157/3A is supplied in 16 lead dual-in-line ceramic packages (F suffix).

Description : Quad 2-INPUT Multiplexer WITH 3-STATE OUTPUTS

Quad 2-INPUT Multiplexer WITH 3-STATE OUTPUTS

The MC74F258A is a Quad 2-input Multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common Data Select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Multiplexer Expansion by Tying Outputs Together
Inverting 3-State Outputs
• AC Enhanced Version of the F258

Description : Quad 2-Input Multiplexer with 3-State Outputs

Quad 2-Input Multiplexer with 3-State Outputs

The MC74AC258/74ACT258 is a Quad 2-input Multiplexer with 3-state outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Multiplexer Expansion by Tying Outputs Together
Inverting 3-State Outputs
• Outputs Source/Sink 24 mA
• ′ACT258 Has TTL Compatible Inputs

Description : HCT158 Quad 2 CHANNEL Multiplexer (INV.) HCT157 Quad 2 CHANNEL Multiplexer

DESCRIPTION
The M54/74HCT157 and the M54/74HCT158 are high speed CMOS Quad 2-CHANNEL Multiplexers fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
These devices consist of four 2-input digital Multiplexers with common select and strobe inputs. The HCT158 is an Inverting Multiplexer while the HCT157 is a non-Inverting Multiplexer. When the STROBE input is held High, selection of data is in hibited and all the outputs become Low in the M74HCT157 and High in the M74HCT158. The SELECT decoding determines whether the A or B in puts get routed to their corresponding Y outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.

■ HIGH SPEED
  tPD = 21 ns (TYP.) AT VCC = 5 V
■ LOW POWER DISSIPATION
  ICC = 4 µA (MAX.) AT TA = 25 °C
■ COMPATIBLE WITH TTL OUTPUTS
  VIH = 2V (MIN.) VIL = 0.8V (MAX)
■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
■ SYMMETRICAL OUTPUT IMPEDANCE
  IOH = IOL = 4 mA (MIN.)
■ BALANCED PROPAGATION DELAYS
  tPLH = tPHL
■ PIN AND FUNCTION COMPATIBLE
   WITH 54/74LS157/158

ON-Semiconductor
ON Semiconductor
Description : Quad 2−Input Multiplexer (Non−Inverting)

The MC10H158 is a Quad two channel Multiplexer with common input select. A “high” level select enables input D00, D10, D20 and D30 and a “low” level select enables input D01, D11, D21 and D31. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay and no increase in power–supply current.
   
• Propagation Delay, 1.5 ns Typical
• Power Dissipation, 197 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
    Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
   

Description : Quad 2 CHANNEL Multiplexer (3-STATE, Inverting)

DESCRIPTION
The M74HC258 is an high speed CMOS Quad 2 CHANNEL Multiplexer (3-STATE) fabricated with silicon gate C2MOS technology.

■ HIGH SPEED : tPD = 11 ns (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 258

ON-Semiconductor
ON Semiconductor
Description : Quad 2-Input Multiplexer (Inverting)

The MC10159 is a Quad two channel Multiplexer with enable. It incorporates common enable and common data select inputs. The select input determines which data inputs are enabled. A high (H) level enables data inputs D00, D10, D20, and D30. A low (L) level enables data inputs D01, D11, D21, and D31. Any change on the data inputs will be reflected at the outputs while the enable is low. Input levels are inverted at the output.

• PD=218 mW typ/pkg (No Load)
• tpd=2.5 ns typ (Data to Q)
• 3.2 ns typ (Select to Q)
• tr, tf=2.5 ns typ (20%–80%)

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