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Part Name(s) : SN54LS171 SN74LS171 SN54LS171J SN54LS171W SN54LS171FK SN74LS171D SN74LS171N TI
Texas Instruments
Description : QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR View

QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

Part Name(s) : HD74LS174 HD74LS174FPEL HD74LS174P HD74LS174RPEL HD74LS175 HD74LS175FPEL HD74LS175P HD74LS175RPEL Renesas
Renesas Electronics
Description : Hex / QUADRUPLE D-TYPE FLIP-FLOPS (WITH CLEAR) View

Hex / QUADRUPLE D-TYPE FLIP-FLOPS (WITH CLEAR)

These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry toimplement D-TYPE flip-flop logic. All have a direct
CLEAR input, and the HD74LS175 features complementary outputs from each FLIP-FLOPS. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.

 

Part Name(s) : SN54AS175A SN54AS175AJ SN74AS175A SN74AS175AD SN74AS175AN SN54AS175AFK TI
Texas Instruments
Description : HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR View

description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-TYPE flip-flop logic.

• ′ALS174 and ′AS174 Contain Six FLIP-FLOPS
   WITH Single-Rail Outputs
• ′ALS175 and ′AS175A Contain Four
   FLIP-FLOPS WITH Double-Rail Outputs
• Buffered Clock and Direct-CLEAR Inputs
• Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
• Fully Buffered Outputs for Maximum
   Isolation From External Disturbances
   (′AS Only)
• Package Options Include Plastic
   Small-Outline (D) Packages, Ceramic Chip
   Carriers (FK), and Standard Plastic (N) and
   Ceramic (J) 300-mil DIPs

Part Name(s) : SN74LV175V TI
Texas Instruments
Description : QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR View

description/ordering information
The ’LV175A devices are QUADRUPLE D-TYPE FLIP-FLOPS designed for 2-V to 5.5-V VCC operation.

● 2-V to 5.5-V VCC Operation
● Max tpd of 7.5 ns at 5 V
● Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
● Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 3.3 V, TA = 25°C
● Support Mixed-Mode Voltage Operation on All Ports
● Contain Four FLIP-FLOPS WITH Double-Rail Outputs
● Applications Include:
    − Buffer/Storage Registers
    − Shift Registers
    − Pattern Generators
● Latch-Up Performance Exceeds 250 mA Per JESD 17
● ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)


Part Name(s) : MM74HC273WM MM74HC273WMX Fairchild
Fairchild Semiconductor
Description : Octal D-TYPE FLIP-FLOPS WITH CLEAR View

General Description
The MM74HC273 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-TYPE flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is functionally as well as pin compatible to the 74LS273. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1 PA maximum
■ Low quiescent current: 80 μA (74 Series)
■ Output drive: 10 LS-TTL loads

 

Part Name(s) : 74LV175A LV175A SN54LV175A SN54LV175AFK SN54LV175AJ SN54LV175AW SN74LV175A SN74LV175ADB SN74LV175ADBR SN74LV175ADGV SN74LV175ANS SNJ54LV175AFK SNJ54LV175AJ SNJ54LV175AW SN74LV175AD SN74LV175ADGVR SN74LV175ADR SN74LV175ANSR SN74LV175APW SN74LV175APWG4 SN74LV175APWR SN74LV175APWT Texas-Instruments
Texas Instruments
Description : QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR View

description/ordering information
The ’LV175A devices are QUADRUPLE D-TYPE FLIP-FLOPS designed for 2-V to 5.5-V VCC operation.

● 2-V to 5.5-V VCC Operation
● Max tpd of 7.5 ns at 5 V
● Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
● Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 3.3 V, TA = 25°C
● Support Mixed-Mode Voltage Operation on All Ports
● Contain Four FLIP-FLOPS WITH Double-Rail Outputs
● Applications Include:
    − Buffer/Storage Registers
    − Shift Registers
    − Pattern Generators
● Latch-Up Performance Exceeds 250 mA Per JESD 17
● ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)

Part Name(s) : 74LS174 74LS175 DM74LS174 DM74LS174M DM74LS174MX DM74LS174N DM74LS174SJ DM74LS174SJX DM74LS175 DM74LS175M DM74LS175MX DM74LS175N DM74LS175SJ DM74LS175SJX DM74LS175CW Fairchild
Fairchild Semiconductor
Description : Hex/Quad D-TYPE FLIP-FLOPS WITH CLEAR View

General Description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-TYPE flip-flop logic. All have a direct CLEAR input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a partic ular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ DM74LS174 contains six FLIP-FLOPS WITH single-rail outputs
■ DM74LS175 contains four FLIP-FLOPS WITH double-rail outputs
■ Buffered clock and direct CLEAR inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW

Part Name(s) : MM74HC174 MM74HC174M MM74HC174MTC MM74HC174MTCX MM74HC174MX MM74HC174N MM74HC174SJ MM74HC174SJX Fairchild
Fairchild Semiconductor
Description : Hex D-TYPE FLIP-FLOPS WITH CLEAR View

General Description
The MM74HC174 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-TYPE flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA (74HC Series)
■ Output drive: 10 LSTTL loads

 

Part Name(s) : DM7474 DM7474N Fairchild
Fairchild Semiconductor
Description : Dual Positive-Edge-Triggered D-TYPE FLIP-FLOPS WITH Preset, CLEAR and Complementary Outputs View

General Description
This device contains two independent positive-edge-triggered D-TYPE FLIP-FLOPS WITH complementary outputs. The information on the D input is accepted by the FLIP-FLOPS on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH WITHout affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or CLEAR inputs will set or reset the outputs regardless of the logic levels of the other inputs.

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