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Description : Hex / QUADRUPLE D-TYPE FLIP-FLOPS (WITH CLEAR)

Hex / QUADRUPLE D-TYPE FLIP-FLOPS (WITH CLEAR)

These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry toimplement D-TYPE flip-flop logic. All have a direct
CLEAR input, and the HD74LS175 features complementary outputs from each FLIP-FLOPS. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.

 

Part Name(s) : HD74LS74 HD74LS74A
Hitachi
Hitachi -> Renesas Electronics
Description : Dual D-TYPE Positive Edge-triggered FLIP-FLOPS(WITH Preset and CLEAR)

Dual D-TYPE Positive Edge-triggered FLIP-FLOPS(WITH Preset and CLEAR)

Description : Octal D-TYPE FLIP-FLOPS WITH CLEAR

General Description
The MM74HC273 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-TYPE FLIP-FLOPS. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.

Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1 μA maximum
■ Low quiescent current: 80 μA (74 Series)
■ Output drive: 10 LS-TTL loads

Fairchild
Fairchild Semiconductor
Description : Octal D-TYPE FLIP-FLOPS WITH CLEAR

General Description
The MM74HC273 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-TYPE flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is functionally as well as pin compatible to the 74LS273. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1 PA maximum
■ Low quiescent current: 80 μA (74 Series)
■ Output drive: 10 LS-TTL loads

 

Part Name(s) : DM7474 DM7474N
Fairchild
Fairchild Semiconductor
Description : Dual Positive-Edge-Triggered D-TYPE FLIP-FLOPS WITH Preset, CLEAR and Complementary Outputs

General Description
This device contains two independent positive-edge-triggered D-TYPE FLIP-FLOPS WITH complementary outputs. The information on the D input is accepted by the FLIP-FLOPS on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH WITHout affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or CLEAR inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Description : Octal D-TYPE Positive-edge-triggered FLIP-FLOPS (WITH CLEAR)

The HD74LS273, positive-edge-triggered FLIP-FLOPS utilize LS TTL circuitry to implement D-TYPE flip-flop logic WITH a direct CLEAR input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse.
When the clock input is at either the high or low level, the D input signal has no effect at the output.

 

Description : Hex/Quad D-TYPE FLIP-FLOPS WITH CLEAR

General Description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-TYPE flip-flop logic. All have a direct CLEAR input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a partic ular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ DM74LS174 contains six FLIP-FLOPS WITH single-rail outputs
■ DM74LS175 contains four FLIP-FLOPS WITH double-rail outputs
■ Buffered clock and direct CLEAR inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW

Description : Hex D-TYPE FLIP-FLOPS WITH CLEAR

General Description
The MM74HC174 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-TYPE flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA (74HC Series)
■ Output drive: 10 LSTTL loads

 

Part Name(s) : 74174 74175
Fairchild
Fairchild Semiconductor
Description : Hex/Quad D FLIP-FLOPS WITH CLEAR

General Description
These positive-edge triggered FLIP-FLOPS utilize TTL circuitry to implement D-TYPE flip-flop logic. All have a direct CLEAR input, and the quad (175) version features complementary outputs from each flip-flop.
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Description : DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

TheSN54/74LS74A dual edge-triggered flip-flop utilizesSchottky TTL circuitryto produce high speed D-TYPE FLIP-FLOPS. Each flip-flop hasindividual CLEAR and set inputs, and also complementary Q and Qoutputs.

Informationat input D is transferred to the Q output on thepositive-going edgeof the clock pulse. Clock triggering occursat a voltage level of the clock pulseand is not directly related to the transition time of the positive-going pulse.When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

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