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QUAD D-TYPE flip flop WITH data ENABLE

The 74AC175/74ACT175 (AC/ACT175) is a high-speed QUAD D-TYPE FLIP-FLOP.

The device is useful for general FLIP-FLOP requirements where CLOCK and clear inputs are common. The information on the D-TYPE inputs is stored during the LOW-to HIGH CLOCK transition. Both true and complemented outputs of each FLIP-FLOP are provided. A Master Reset input resets all FLIP-FLOPs, independent of the CLOCK or D-TYPE inputs, when LOW.

CLOCK DRIVER QUAD D-TYPE FLIP-FLOP WITH MATCHED PROPAGATION DELAYS

The MC74F803 is a high-speed, low-power, QUAD D-TYPE FLIP-FLOP featuring separate D-TYPE inputs, and inverting outputs WITH closely matched propagation delays. WITH a buffered CLOCK (CP) input that is common to all FLIP-FLOPs, the F803 is useful in high-frequency systems as a CLOCK driver, providing multiple outputs that are synchronous. Because of the matched propagation delays, the duty cycles of the output waveforms in a CLOCK driver application are symmetrical WITHin 1.0 to 1.5 nanoseconds.

• Edge-Triggered D-TYPE Inputs
• Buffered Positive Edge-Triggered CLOCK
• Matched Outputs for Synchronous CLOCK Driver Applications
• Outputs Guaranteed for Simultaneous Switching

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-TYPE FLIP-FLOPs WITH a buffered common CLOCK and a buffered common CLOCK ENABLE. The SN54/74LS378 is a 6-Bit Register WITH a buffered common ENABLE.
This device is similar to the SN54/74LS174, but WITH common ENABLE rather than common Master Reset. The SN54/74LS379 is a 4-Bit Register WITH buffered common ENABLE.
This device is similar to the SN54/74LS175 but features the common ENABLE rather then common Master Reset.

• 8-Bit High Speed Parallel Registers
• Positive Edge-Triggered D-TYPE Flip Flops
• Fully Buffered Common CLOCK and ENABLE Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects

CLOCK DRIVER
QUAD D-TYPE FLIP-FLOP
WITH MATCHED PROPAGATION DELAYS

The MC74F1803 is a high–speed, low–power, QUAD D–type flip–flop featuring separate D–type inputs and inverting outputs WITH closely matched propagation delays. WITH a buffered CLOCK (CP) input that is common to all flip–flops, the MC74F1803 is useful in high–frequency systems as a CLOCK driver, providing multiple outputs that are synchronous. Because of the matched propagation delays, the duty cycles of the output waveforms in a
CLOCK driver application are symmetrical WITHin 2.0 nanoseconds.

• Edge–Triggered D–Type Inputs
• Buffered Positive Edge–Triggered CLOCK
• Matched Outputs for Synchronous CLOCK Driver Applications
• Outputs Guaranteed for Simultaneous Switching

Octal D Flip−Flop WITH CLOCK ENABLE

The MC74AC377/74ACT377 has eight edge-triggered, D-TYPE FLIP-FLOPs WITH individual D inputs and Q outputs. The common buffered CLOCK (CP) input loads all FLIP-FLOPs simultaneously, when the CLOCK ENABLE (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH CLOCK transition, is transferred to the corresponding FLIP-FLOP’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH CLOCK transition for predictable operation.

Features
• Ideal for Addressable Register Applications
• CLOCK ENABLE for Address and Data Synchronization Applications
• Eight Edge-Triggered D FLIP-FLOPs
• Buffered Common CLOCK
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• MSL = 1 for all Surface Mount
• Chip Complexity: 292 FETs or 73 Gates
• Pb−Free Packages are Available

Description
The HD74AC175 is a high-speed QUAD D FLIP-FLOP. The device is useful for general FLIP-FLOP requirements where CLOCK and clear inputs are common. The information on the D inputs is stored during the Low-to-High CLOCK transition. Both true and complemented outputs of each FLIP-FLOP are provided. A Master Reset input resets all FLIP-FLOPs, independent of the CLOCK or D inputs, when Low.

Features
• Edge-Triggered D-TYPE Inputs
• Buffered Positive Edge-Triggered CLOCK
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA

General Description
The 74F175 is a high-speed QUAD D-TYPE FLIP-FLOP. The device is useful for general FLIP-FLOP requirements where CLOCK and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH CLOCK transition.
Both true and complemented outputs of each FLIP-FLOP are provided. A Master Reset input resets all FLIP-FLOPs, independent of the CLOCK or D inputs, LOW.

Features
■ Edge-triggered D-TYPE inputs
■ Buffered positive edge-triggered CLOCK
■ Asynchronous common reset
■ True and complement output

General Description
The ABT377 has eight edge-triggered, D-TYPE FLIP-FLOPs WITH individual D inputs and Q outputs. The common buffered CLOCK (CP) input loads all FLIP-FLOPs simultaneously when the CLOCK ENABLE (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH CLOCK transition, is transferred to the corresponding FLIP-FLOP’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH CLOCK transition for predictable operation.

Features
■ CLOCK ENABLE for address and data synchronization applications
■ Eight edge-triggered D-TYPE FLIP-FLOPs
■ Buffered common CLOCK
■ See ABT273 for master reset version
■ See ABT373 for transparent latch version
■ See ABT374 for 3-STATE version
■ Output sink capability of 64 mA, source capability of 32 mA
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
   power up and power down cycle
■ Non-destructive hot insertion capability
■ Disable time less than ENABLE time to avoid bus contention

Description
The HD74AC175 is a high-speed QUAD D FLIP-FLOP. The device is useful for general FLIP-FLOP requirements where CLOCK and clear inputs are common. The information on the D inputs is stored during the Low-to-High CLOCK transition. Both true and complemented outputs of each FLIP-FLOP are provided. A Master Reset input resets all FLIP-FLOPs, independent of the CLOCK or D inputs, when Low.

Features
• Edge-Triggered D-TYPE Inputs
• Buffered Positive Edge-Triggered CLOCK
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA