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Part Name(s) : 74LS645 74LS645-1 HD74LS645-1 Hitachi
Hitachi -> Renesas Electronics
Description : OCTAL Bus Transceivers(non-inverted-3STATE OUTPUTS) View

OCTAL Bus Transceivers(non-inverted-3STATE OUTPUTS)

Part Name(s) : 74LVX374MSCX Fairchild
Fairchild Semiconductor
Description : Low Voltage OCTAL D-Type Flip-Flop WITH 3-STATE OUTPUTS View

General Description
The LVX374 is a high-speed, low-power OCTAL D-type FLIPFLOP featuring separate D-type inputs for each flip-flop and 3-STATE OUTPUTS for bus-oriented applications.
   
Features
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
    dynamic threshold performance
   

Part Name(s) : 74LVX374 74LVX374M 74LVX374MTC 74LVX374SJ 74LVX374MX 74LVX374SJX 74LVX374MTCX Fairchild
Fairchild Semiconductor
Description : Low Voltage OCTAL D-Type Flip-Flop WITH 3-STATE OUTPUTS View

General Description
The LVX374 is a high-speed, low-power OCTAL D-type FLIPFLOP featuring separate D-type inputs for each flip-flop and 3-STATE OUTPUTS for bus-oriented applications.
   
Features
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
    dynamic threshold performance
   

Part Name(s) : 74F374 74F374MSA 74F374MSAX 74F374PC 74F374SC 74F374SCX 74F374SJ 74F374SJX 74F374 74F374MSA 74F374SC 74F374SJ 74F374SCX 74F374SJX 74F374MSAX 74F374PC Fairchild
Fairchild Semiconductor
Description : OCTAL D-Type Flip-Flop WITH 3-STATE OUTPUTS View

General Description
The 74F374 is a high-speed, low-power OCTAL D-type FLIPFLOP featuring separate D-type inputs for each flip-flop and 3-STATE OUTPUTS for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all FLIPFLOPs.

Features
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ 3-STATE OUTPUTS for bus-oriented applications
■ Guaranteed 4000V minimum ESD protection


Part Name(s) : IN74ALS240A IN74ALS240AD IN74ALS240AN IN74LS240AN INTE-ElectronicGRAL
Integral Corp.
Description : OCTAL BUFFER / DRIVER WITH 3-STATE OUTPUTS View

OCTAL BUFFER / DRIVER WITH 3-STATE OUTPUTS

This OCTAL buffer/driver is designed specially to improve both the performance and density of 3-state memory address drivers, clock drivers and bus oriented receivers and transmitters. When this device is used WITH the ‘ALS241, ‘AS241A, ‘ALS244 and AS244A, the circuit designer has a choice of selected combinations of inverting and noninverting OUTPUTS, symmetrical active-low output-enable (OE) inputs and complementary OE and OE inputs. This device features high fan-out and improved fan-in.
The IN74ALS240A is characterized for operation from 0°C to 70°C.

Part Name(s) : HD74LS645FPEL HD74LS645P HD74LS645 Renesas
Renesas Electronics
Description : OCTAL Bus Transceivers (non-inverted 3-state OUTPUTS) View

OCTAL Bus Transceivers (non-inverted 3-state OUTPUTS)

This OCTAL bus transceivers is designed for asynchronous two-way communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the buses are effectively isolated.

Part Name(s) : MC74ACT534 MC74AC534 MC74ACT534N MC74AC534N MC74ACT534DW MC74AC534DW Motorola
Motorola => Freescale
Description : OCTAL D-Type Flip-Flop WITH 3-State OUTPUTS View

OCTAL D-Type Flip-Flop WITH 3-State OUTPUTS

The MC74AC534/74ACT534 is a high-speed, low-power OCTAL D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state OUTPUTS for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip flops. The ′AC/ACT534 is the same as the ′AC/ACT374 except that the OUTPUTS are inverted.

• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• 3-State OUTPUTS for Bus Oriented Applications

Part Name(s) : MC74ACT374ML2 MC74ACT374MR2 MC74ACT374DTEL MC74ACT374ML1 ON-Semiconductor
ON Semiconductor
Description : OCTAL D-Type Flip-Flop WITH 3-State OUTPUTS View

OCTAL D-Type Flip-Flop WITH 3-State OUTPUTS

The MC74AC374/74ACT374 is a high-speed, low-power OCTAL D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state OUTPUTS for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.

• Buffered Positive Edge-Triggered Clock
• 3-State OUTPUTS for Bus-Oriented Applications
OUTPUTS Source/Sink 24 mA
• See MC74AC273 for Reset Version
• See MC74AC377 for Clock Enable Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC574 for Broadside Pinout Version
• See MC74AC564 for Broadside Pinout Version WITH Inverted OUTPUTS
• ′ACT374 Has TTL Compatible Inputs

Part Name(s) : SN74LS373 SN74LS373DW SN74LS373DWR2 SN74LS373H SN74LS373M SN74LS373MEL SN74LS373ML1 SN74LS373ML2 SN74LS373MR1 SN74LS373N SN74LS374 SN74LS374DW SN74LS374DWR2 SN74LS374M SN74LS374MEL SN74LS374MR1 SN74LS374N ON-Semiconductor
ON Semiconductor
Description : OCTAL Transparent Latch WITH 3-State OUTPUTS; OCTAL D-Type Flip-Flop WITH 3-STATE OUTPUT View

OCTAL Transparent Latch WITH 3-State OUTPUTS; OCTAL D-Type Flip-Flop WITH 3-State Output

The SN74LS373 consists of eight latches WITH 3-state OUTPUTS for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OEis HIGH the bus output is in the high impedance state.
The SN74LS374 is a high-speed, low-power OCTAL D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state OUTPUTS for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced Low Power Schottky technology and is compatible WITH all ON Semiconductor TTL families.

•Eight Latches in a Single Package
•3-State OUTPUTS for Bus Interfacing
•Hysteresis on Latch Enable
•Edge-Triggered D-Type Inputs
•Buffered Positive Edge-Triggered Clock
•Hysteresis on Clock Input to Improve Noise Margin
•Input Clamp Diodes Limit High Speed Termination Effects

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