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Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% Pin-out retention.
The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% Pin-out retention
◆ High speed
    — 7.5ns tPD Commercial and 10ns tPD Industrial
    — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 Pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Bus-FriendlyTM inputs and I/Os
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
    — Supports HDL design methodologies with results optimized for MACH 4
    — Flexibility to adapt to user requirements
    — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
    — LatticePROTM software for in-system programmability support on PCs and automated test equipment
    — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

Description : ispMACH™ 4A CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% Pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
   
FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices
        for 100% routability and 100% Pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 Pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
    — Supports HDL design methodologies with results optimized
        for ispMACH 4A
    — Flexibility to adapt to user requirements
    — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
    — LatticePROTM software for in-system programmability support
        on PCs and automated test equipment
    — Programming support on all major programmers
        including Data I/O, BP Microsystems, Advin,
        and System General
   

Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% Pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    — Excellent First-Time-FitTM and refit feature
    — SpeedLockingTM performance for guaranteed fixed timing
    — Central, input and output switch matrices for 100% routability and 100% Pin-out retention
◆ High speed
    — 5.0ns tPD Commercial and 7.5ns tPD Industrial
    — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 Pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
    — D/T registers and latches
    — Synchronous or asynchronous mode
    — Dedicated input registers
    — Programmable polarity
    — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
    — 3.3-V & 5-V JEDEC-compliant operations
    — JTAG (IEEE 1149.1) compliant for boundary scan testing
    — 3.3-V & 5-V JTAG in-system programming
    — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
    — Safe for mixed supply voltage system designs
    — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
    — Hot-socketing
    — Programmable security bit
    — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Lead-free package options

Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% Pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices for 100% routability and 100% Pin-out retention
◆ High speed
   — 5.0ns tPD Commercial and 7.5ns tPD Industrial
   — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 Pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG in-system programming
   — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
   — Hot-socketing
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for ispMACH 4A
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for in-system programmability support on PCs
         and automated test equipment
   — Programming support on all major programmers including Data I/O, BP Microsystems,
         Advin, and System General

Philips
Philips Electronics
Description : OM8371 / OM8371PS 64 Pin

Philips OM8371PS/N3/1/1867

Description : High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% Pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices for 100% routability and 100% Pin-out retention
◆ High speed
   — 5.0ns tPD Commercial and 7.5ns tPD Industrial
   — 182MHz fCNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 Pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG in-system programming
   — PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Programmable pull-up or Bus-FriendlyTM inputs and I/Os
   — Hot-socketing
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for ispMACH 4A
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for in-system programmability support on PCs
         and automated test equipment
   — Programming support on all major programmers including Data I/O, BP Microsystems,
         Advin, and System General

Description : MODULAR JACKS AND PLUGS: GMX-SMT2 Series Surface Mount Modular Jack

[KYCON]

Product Features
    Low Profile Design Suitable for PC Add-On
    Board Applications
    Available in 4, 6, 8, and 10 Position Housings
    Available Fully Shielded for EMI/RFI Protection
    CSA/NRTL Certified File No. LR78160
    UL File No. E134345
   

Description : High-performance E2CMOS in-system programmable logic, 5-V VCC, 32 macrocells, 32 I/Os, 12ns

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
    - Excellent First-Time-FitTM and refit feature
    - SpeedLocking performance for guaranteed fixed timing
    - Central, input and output switch matrices for 100% routability and 100% Pin-out retention
◆ High speed
    - 7.5ns tPD Commercial and 10ns tPD Industrial
    - 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 Pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
    - D/T registers and latches
    - Synchronous or asynchronous mode
    - Dedicated input registers
    - Programmable polarity
    - Reset/ preset swapPing

Description : MACH 4 CPLD Family High Performance E2CMOS® In-System Programmable Logic

GENERAL DESCRIPTION
The MACH® 4 family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% Pin-out retention. The MACH 4 family offer 5-V (M4-xxx) and 3.3-V (M4LV-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

FEATURES
◆ High-performance, E2CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
   — Excellent First-Time-FitTM and refit feature
   — SpeedLockingTM performance for guaranteed fixed timing
   — Central, input and output switch matrices
      for 100% routability and 100% Pin-out retention
◆ High speed
   — 7.5ns tPD Commercial and 10ns tPD Industrial
   — 111.1MHz fCNT
◆ 32 to 256 macrocells; 32 to 384 registers
◆ 44 to 256 Pins in PLCC, PQFP, TQFP and BGA packages
◆ Flexible architecture for a wide range of design styles
   — D/T registers and latches
   — Synchronous or asynchronous mode
   — Dedicated input registers
   — Programmable polarity
   — Reset/ preset swapPing
◆ Advanced capabilities for easy system integration
   — 3.3-V & 5-V JEDEC-compliant operations
   — JTAG (IEEE 1149.1) compliant for boundary scan testing
   — 3.3-V & 5-V JTAG in-system programming
   — PCI compliant (-7/-10/-12 speed grades)
   — Safe for mixed supply voltage system designs
   — Bus-FriendlyTM inputs and I/Os
   — Programmable security bit
   — Individual output slew rate control
◆ Advanced E2CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERTTM software for rapid logic development
   — Supports HDL design methodologies with results optimized for MACH 4
   — Flexibility to adapt to user requirements
   — Software partnerships that ensure customer success
◆ Lattice and third-party hardware programming support
   — LatticePROTM software for in-system programmability support
      on PCs and automated test equipment
   — Programming support on all major programmers including Data I/O,
      BP Microsystems, Advin, and System General

Description : Coaxial cable connection of Antennas, Sensors, and Communication Trunk Lines

Termination of coaxial cables in automotive, medical and instrumentation applications utilizes one step to crimp the center conductor, shield and outer insulation.

Features
● Cost efficient termination
    Highly efficient and reliable one step crimp termination allows high volume production with semiautomatic equipment.
● Space-saving Design
    Compact and light weight comparing with HRS GT5 series.

Applications
    automotive audio systems.

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