datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P/N + Description + Content Search

Search Word's :
Motorola
Motorola => Freescale
Description : DUAL D-TYPE POSITIVE EDGE-TRIGGERED Flip-Flop Low Power SCHOTTKY

DUAL D-TYPE POSITIVE EDGE-TRIGGERED Flip-Flop

The SN54/74LS74A dual edge-triggered Flip-Flop utilizes Schottky TTL circuitry to produce high speed D-type Flip-Flops. Each Flip-Flop has individual clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the Low level, the D input signal has no effect.

Description : Hex D-Type Flip-Flop Quad D-Type Flip-Flop

General Description
The CD40174BC consists of six positive-edge triggered D type Flip-Flops; the true outputs from each Flip-Flop are externally available. The CD40175BC consists of four positive edge triggered D-type Flip-Flops; both the true and comple ment outputs from each Flip-Flop are externally available.
All Flip-Flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all
Q outputs to logical “0” and Qs (CD40175BC only) to logical “1”. All inputs are protected from static discharge by diode clamps to VDDand VSS.

Features
■ Wide supply voltage range: 3V to 15V
■ High noise immunity: 0.45 VDD(typ.)
Low Power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS
■ Equivalent to MC14174B, MC14175B
■ Equivalent to MM74C174, MM74C175

Description : Low Power Triple D-Type Flip-Flop

General Description
The 100331 contains three D-type, edge-triggered master/slave Flip-Flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each Flip-Flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CP n and CPC are Low and transfers to a slave when CP n or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down resistors.

Features
■ 35% Power reduction of the 100131
■ 2000V ESD protection
■ Pin/function compatible with 100131
■ Voltage compensated operating range = −4.2V to −5.7V
■ Available to industrial grade temperature range

Fairchild
Fairchild Semiconductor
Description : Hex/Quad D Flip-Flop with Clear

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type Flip-Flop logic. All have a direct clear input, and the quad (DM74S175) versions feature comple mentary outputs from each Flip-Flop.

Features
■DM74S174 contain six Flip-Flops with single-rail outputs.
■DM74S175 contain four Flip-Flops with double-rail outputs.
■Buffered clock and direct clear inputs
■Individual data input to each Flip-Flop
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical Power dissipation per Flip-Flop 75mW

Fairchild
Fairchild Semiconductor
Description : Quad D-Type Flip-Flop

The 74AC175/74ACT175 (AC/ACT175) is a high-speed quad D-type Flip-Flop.

The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the Low-to HIGH clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D-type inputs, when Low.

Integral
Integral Corp.
Description : OCTAL D-TYPE Flip-Flop WITH CLEAR

DESCRIPTION
This monolithic, positive-edge-triggered Flip-Flop utilizes TTL circuitry to implement D-type Flip-Flop logic with a direct clear input.

• Contains Eight Flip-Flops with Single-Rail Outputs
• Buffered Clock and Direct Clear Inputs
• Individual Data Input to Each Flip-Flop
• Applications Include:
    Buffer/Storage Registers
    Shift Registers
    Pattern Generators

Part Name(s) : DM74LS534 DM74LS534N
Fairchild
Fairchild Semiconductor
Description : Octal D-Type Flip-Flop with 3-STATE Outputs

General Description
The DM74LS534 is a high speed, Low Power octal D-type Flip-Flop featuring separate D-type inputs for each Flip-Flop and 3-STATE outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all Flip-Flops. The DM74LS534 is the same as the DM74LS374 except that the outputs are inverted.

 

Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED Flip-Flop

DUAL JK POSITIVE EDGE-TRIGGERED Flip-Flop Low Power SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JK Flip-Flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignalLows operation as a D Flip-Flop by simply connecting the J and Kpins together.

Part Name(s) : HD74AC175
Hitachi
Hitachi -> Renesas Electronics
Description : Quad D-Type Flip-Flop

Description
The HD74AC175 is a high-speed quad D Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D inputs, when Low.

Features
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA

Renesas
Renesas Electronics
Description : Quad D-Type Flip-Flop

Description
The HD74AC175 is a high-speed quad D Flip-Flop. The device is useful for general Flip-Flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both true and complemented outputs of each Flip-Flop are provided. A Master Reset input resets all Flip-Flops, independent of the Clock or D inputs, when Low.

Features
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA

12345678910 Next

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]