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Part Name(s) : HD74LS174 HD74LS174FPEL HD74LS174P HD74LS174RPEL HD74LS175 HD74LS175FPEL HD74LS175P HD74LS175RPEL Renesas
Renesas Electronics
Description : Hex / Quadruple D-type FLIP-FLOPS (WITH CLEAR) View

Hex / Quadruple D-type FLIP-FLOPS (WITH CLEAR)

These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry toimplement D-type flip-flop logic. All have a direct
CLEAR input, and the HD74LS175 features complementary outputs from each FLIP-FLOPS. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.

 

Part Name(s) : 74LS174 74LS175 DM74LS174 DM74LS174M DM74LS174MX DM74LS174N DM74LS174SJ DM74LS174SJX DM74LS175 DM74LS175M DM74LS175MX DM74LS175N DM74LS175SJ DM74LS175SJX DM74LS175CW Fairchild
Fairchild Semiconductor
Description : HEX/QUAD D-Type FLIP-FLOPS WITH CLEAR View

General Description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-type flip-flop logic. All have a direct CLEAR input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a partic ular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ DM74LS174 contains six FLIP-FLOPS WITH single-rail outputs
■ DM74LS175 contains four FLIP-FLOPS WITH double-rail outputs
■ Buffered clock and direct CLEAR inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW

Part Name(s) : DM74S174 DM74S174N DM74S175 DM74S175N Fairchild
Fairchild Semiconductor
Description : HEX/QUAD D Flip-Flop WITH CLEAR View

General Description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-type flip-flop logic. All have a direct CLEAR input, and the quad (DM74S175) versions feature comple mentary outputs from each flip-flop.

Features
■DM74S174 contain six FLIP-FLOPS WITH single-rail outputs.
■DM74S175 contain four FLIP-FLOPS WITH double-rail outputs.
■Buffered clock and direct CLEAR inputs
■Individual data input to each flip-flop
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical power dissipation per flip-flop 75mW

Part Name(s) : 54174 54174DMQB 54174FMQB 54175 54175DMQB 54175FMQB DM54174 DM54174J DM54174W DM54175 DM54175J DM54175W DM74174 DM74174N DM74175 DM74175N DM54174J/883 DM54LS174J-MLS DM54LS174J/883 DM54LS174MW8 DM54LS174W/883 National-Semiconductor
National ->Texas Instruments
Description : HEX/QUAD D FLIP-FLOPS WITH CLEAR View

General Description
These positive-edge triggered FLIP-FLOPS utilize TTL circuitry to implement D-type flip-flop logic. All have a direct CLEAR input, and the quad (175) version features complementary outputs from each flip-flop.

Features
■ 174 contains six FLIP-FLOPS WITH single-rail outputs
■ 175 contains four FLIP-FLOPS WITH double-rail outputs
■ Buffered clock and direct CLEAR inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 38 mW
■ Alternate Military/Aerospace device (54174, 54175) is available.
   Contact a National Semiconductor Sales
   Of fice/Distributor for specifications.


Part Name(s) : SN54AS175A SN54AS175AJ SN74AS175A SN74AS175AD SN74AS175AN SN54AS175AFK TI
Texas Instruments
Description : HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR View

description
These positive-edge-triggered FLIP-FLOPS utilize TTL circuitry to implement D-type flip-flop logic.

• ′ALS174 and ′AS174 Contain Six FLIP-FLOPS
   WITH Single-Rail Outputs
• ′ALS175 and ′AS175A Contain Four
   FLIP-FLOPS WITH Double-Rail Outputs
• Buffered Clock and Direct-CLEAR Inputs
• Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
• Fully Buffered Outputs for Maximum
   Isolation From External Disturbances
   (′AS Only)
• Package Options Include Plastic
   Small-Outline (D) Packages, Ceramic Chip
   Carriers (FK), and Standard Plastic (N) and
   Ceramic (J) 300-mil DIPs

Part Name(s) : MM74HC174 MM74HC174M MM74HC174MTC MM74HC174MTCX MM74HC174MX MM74HC174N MM74HC174SJ MM74HC174SJX Fairchild
Fairchild Semiconductor
Description : Hex D-Type FLIP-FLOPS WITH CLEAR View

General Description
The MM74HC174 edge triggered FLIP-FLOPS utilize advanced silicon-gate CMOS technology to implement D-type flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA (74HC Series)
■ Output drive: 10 LSTTL loads

 

Part Name(s) : HD74HC175 Hitachi
Hitachi -> Renesas Electronics
Description : Quad. D-typ FLIP-FLOPS (WITH CLEAR) View

Description
Information at the D inputs of the HD74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip flops are controlled by a common clock and a common CLEAR. CLEARing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are CLEARed to a logic low level and all four Q outputs to a logic high level.

Features
• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Part Name(s) : HD74HC174 Hitachi
Hitachi -> Renesas Electronics
Description : Hex D-type FLIP-FLOPS (WITH CLEAR) View

Description
This device contains 6 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The CLEAR input when low, sets all outputs to a low state.

Features
•  High Speed Operation: tpd(Clock to Q) = 15 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Part Name(s) : HD74LV174A Hitachi
Hitachi -> Renesas Electronics
Description : Hex D-type FLIP-FLOPS WITH CLEAR View

Description
This device contains 6 master-slave FLIP-FLOPS WITH a common clock and common CLEAR. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The CLEAR input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.

Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

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