datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P/N + Description + Content Search

Search Word's :
Description : Hex / Quadruple D-type Flip-Flops (with Clear)

Hex / Quadruple D-type Flip-Flops (with Clear)

These positive-edge-triggered Flip-Flops utilize TTL circuitry toimplement D-type flip-flop logic. All have a direct
Clear input, and the HD74LS175 features complementary outputs from each Flip-Flops. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.

 

Part Name(s) : 74174 74175
Fairchild
Fairchild Semiconductor
Description : Hex/Quad D Flip-Flops with Clear

General Description
These positive-edge triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct Clear input, and the quad (175) version features complementary outputs from each flip-flop.
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Description : Hex/Quad D-Type Flip-Flops with Clear

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct Clear input, and the quad (175) versions feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time require ments is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a partic ular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ DM74LS174 contains six Flip-Flops with single-rail outputs
■ DM74LS175 contains four Flip-Flops with double-rail outputs
■ Buffered clock and direct Clear inputs
■ Individual data input to each flip-flop
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per flip-flop 14 mW

Fairchild
Fairchild Semiconductor
Description : Hex/Quad D Flip-Flop with Clear

General Description
These positive-edge-triggered Flip-Flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct Clear input, and the quad (DM74S175) versions feature comple mentary outputs from each flip-flop.

Features
■DM74S174 contain six Flip-Flops with single-rail outputs.
■DM74S175 contain four Flip-Flops with double-rail outputs.
■Buffered clock and direct Clear inputs
■Individual data input to each flip-flop
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical power dissipation per flip-flop 75mW

Description : Hex D-Type Flip-Flops with Clear

General Description
The MM74HC174 edge triggered Flip-Flops utilize advanced silicon-gate CMOS technology to implement D-type flip flops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave Flip-Flops with a common clock and common Clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The Clear input when LOW, sets all outputs to a low state.
Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features
■ Typical propagation delay: 16 ns
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA (74HC Series)
■ Output drive: 10 LSTTL loads

 

Part Name(s) : HD74HC175
Hitachi
Hitachi -> Renesas Electronics
Description : Quad. D-typ Flip-Flops (with Clear)

Description
Information at the D inputs of the HD74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip flops are controlled by a common clock and a common Clear. Clearing is accomplished by a negative pulse at the Clear input. All four Q outputs are Cleared to a logic low level and all four Q outputs to a logic high level.

Features
• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

Part Name(s) : HD74HC174
Hitachi
Hitachi -> Renesas Electronics
Description : Hex D-type Flip-Flops (with Clear)

Description
This device contains 6 master-slave Flip-Flops with a common clock and common Clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The Clear input when low, sets all outputs to a low state.

Features
•  High Speed Operation: tpd(Clock to Q) = 15 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Renesas
Renesas Electronics
Description : Hex D-type Flip-Flops (with Clear)

Description
This device contains 6 master-slave Flip-Flops with a common clock and common Clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The Clear input when low, sets all outputs to a low state.

Features
•  High Speed Operation: tpd(Clock to Q) = 15 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Renesas
Renesas Electronics
Description : Quad. D-type Flip-Flops (with Clear)

Description
Information at the D inputs of the HD74HC175 is transferred to the Q and Qoutputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four Flip-Flops are controlled by a common clock and a common Clear. Clearing isaccomplished by a negative pulse at the Clear input. All four Q outputs are Cleared to a logic low level and all four Qoutputs to a logic high level.

Features
•  High Speed Operation: tpd(Clock to Q) = 14 ns typ (CL= 50 pF)
•  High Output Current: Fanout of 10 LSTTL Loads
•  Wide Operating Voltage: VCC= 2 to 6 V
•  Low Input Current: 1 µA max
•  Low Quiescent Supply Current: ICC(static) = 4 µA max (Ta = 25°C)

Philips
Philips Electronics
Description : Hex D Flip-Flops

DESCRIPTION
The 74F174 has six edge-triggered D-type Flip-Flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (Clear) all Flip-Flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

FEATURES
• Six edge-triggered D-type Flip-Flops
• Buffered common Clock
• Buffered, asynchronous Master Reset

 

12345678910 Next

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]