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Part Name(s) : DM74S174 DM74S174N DM74S175 DM74S175N Fairchild
Fairchild Semiconductor
Description : HEX/Quad D FLIP-FLOP WITH CLEAR

General Description
These positive-edge-triggered FLIP-FLOPs utilize TTL circuitry to implement D-TYPE FLIP-FLOP logic. All have a direct CLEAR input, and the quad (DM74S175) versions feature comple mentary outputs from each FLIP-FLOP.

Features
■DM74S174 contain six FLIP-FLOPs WITH single-rail outputs.
■DM74S175 contain four FLIP-FLOPs WITH double-rail outputs.
■Buffered clock and direct CLEAR inputs
■Individual data input to each FLIP-FLOP
■Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■Typical clock frequency 110 MHz
■Typical power dissipation per FLIP-FLOP 75mW

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Part Name(s) : CD40174BC CD40174BCM CD40175BCM CD40175BCN MC14174B MC14175B MM74C175 CD40174BCMX CD40174BCN CD40175BC CD40175BCMX Fairchild
Fairchild Semiconductor
Description : HEX D-TYPE FLIP-FLOP Quad D-TYPE FLIP-FLOP

General Description
The CD40174BC consists of six positive-edge triggered D type FLIP-FLOPs; the true outputs from each FLIP-FLOP are externally available. The CD40175BC consists of four positive edge triggered D-TYPE FLIP-FLOPs; both the true and comple ment outputs from each FLIP-FLOP are externally available.
All FLIP-FLOPs are controlled by a common clock and a common CLEAR. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The CLEARing operation, enabled by a negative pulse at CLEAR input, CLEARs all
Q outputs to logical “0” and Qs (CD40175BC only) to logical “1”. All inputs are protected from static discharge by diode clamps to VDDand VSS.
Features
■ Wide supply voltage range: 3V to 15V
■ High noise immunity: 0.45 VDD(typ.)
■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS
■ Equivalent to MC14174B, MC14175B
■ Equivalent to MM74C174, MM74C175

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Part Name(s) : HD74LS174 HD74LS174FPEL HD74LS174P HD74LS174RPEL HD74LS175 HD74LS175FPEL HD74LS175P HD74LS175RPEL Renesas
Renesas Electronics
Description : HEX / Quadruple D-TYPE FLIP-FLOPs (WITH CLEAR)

HEX / Quadruple D-TYPE FLIP-FLOPs (WITH CLEAR)

These positive-edge-triggered FLIP-FLOPs utilize TTL circuitry toimplement D-TYPE FLIP-FLOP logic. All have a direct
CLEAR input, and the HD74LS175 features complementary outputs from each FLIP-FLOPs. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the outputs.

 

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Part Name(s) : DM74174 54174DMQB 54174FMQB 54175DMQB 54175FMQB DM54174J DM54174W DM54175J DM54175W DM74174 DM74174N DM74175 DM74175N Fairchild
Fairchild Semiconductor
Description : HEX/Quad D-TYPE FLIP-FLOP WITH CLEAR

General Description
These positive-edge triggered FLIP-FLOPs utilize TTL circuitry to implement D-TYPE FLIP-FLOP logic. All have a direct CLEAR input.
Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.

Features
■ Contains six FLIP-FLOPs WITH single-rail outputs
■ Buffered clock and direct CLEAR inputs
■ Individual data input to each FLIP-FLOP
■ Applications include:
   Buffer/storage registers
   Shift registers
   Pattern generators
■ Typical clock frequency 40 MHz
■ Typical power dissipation per FLIP-FLOP 38 mW

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Part Name(s) : M74HC174 M74HC174B1R M74HC174M1R M74HC174RM13TR M74HC174TTR ST-Microelectronics
STMicroelectronics
Description : HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION
The M74HC174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated WITH silicon gate C2MOS technology.
   
■ HIGH SPEED :
    fMAX = 66MHz (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
    ICC =4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
    VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL = 4mA (MIN)
■ BALANCED PROPAGATION DELAYS:
    tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE:
    VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH
    74 SERIES 174
   

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Part Name(s) : SN74F174 SN74F174A SN74F174AD SN74F174ADE4 SN74F174ADR SN74F174ADRE4 SN74F174AN F174A Texas-Instruments
Texas Instruments
Description : HEX D-TYPE FLIP-FLOP WITH CLEAR

description
This monolithic, positive-edge-triggered FLIP-FLOP utilizes TTL circuitry to implement D-TYPE FLIP-FLOP logic WITH a direct CLEAR (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C.

• Contains Six FLIP-FLOPs WITH Single-Rail
   Outputs
• Buffered Clock and Direct CLEAR Inputs
• Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
• Fully Buffered Outputs for Maximum
   Isolation From External Disturbances
• Package Options Include Plastic
   Small-Outline Packages and Standard
   Plastic 300-mil DIPs

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Part Name(s) : M81016 M81016FP M81016KP M81016P Mitsubishi
MITSUBISHI ELECTRIC
Description : OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR

M81016 is octal D-TYPE FLIP-FLOP driver by 20-pin package. It has 8 same circuit units which is composed of D-TYPE FLIP-FLOP logic circuit and high voltage NchMOS output transistor. M81016 has a common direct CLEAR input and a common clock input.

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Part Name(s) : SN74F174 SN74F174A SN74F174AD SN74F174ADE4 SN74F174ADG4 SN74F174ADR SN74F174ADRE4 SN74F174ADRG4 SN74F174AN SN74F174ANE4 SN74F174ANSR SN74F174ANSRE4 SN74F174ANSRG4 TI
Texas Instruments
Description : HEX D-TYPE FLIP-FLOP WITH CLEAR

description
This monolithic, positive-edge-triggered FLIP-FLOP utilizes TTL circuitry to implement D-TYPE FLIP-FLOP logic WITH a direct CLEAR (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C.

● Contains Six FLIP-FLOPs WITH Single-Rail Outputs
● Buffered Clock and Direct CLEAR Inputs
● Applications Include:
   Buffer/Storage Registers
   Shift Registers
   Pattern Generators
● Fully Buffered Outputs for Maximum Isolation From External Disturbances
● Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

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Part Name(s) : 74VHC174M 74VHC174T 74VHC174_99 ST-Microelectronics
STMicroelectronics
Description : HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION
The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology.
Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse.
When the CLEAR input is held low, the Q outputs are held low independentlyof the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs WITH no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   fMAX =175 MHz (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 oC
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ POWERDOWN PROTECTIONON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.8V(Max.)

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Part Name(s) : 74VHC174 74VHC174MTR 74VHC174TTR ST-Microelectronics
STMicroelectronics
Description : HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION
The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated WITH sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse.
When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs WITH no regard to the supply voltage. This device can be used to interface 5V to 3V.
All inputs and outputs are equipped WITH protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED:
   fMAX = 175MHz (TYP.) at VCC = 5V
■ LOW POWER DISSIPATION:
   ICC = 4 µA (MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
   VNIH = VNIL = 28% VCC (MIN.)
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGE RANGE:
   VCC(OPR) = 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: VOLP = 0.8V (MAX.)

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