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Part Name(s) : 74HC 74HC109 74HCT109 74HC/HCT109 Philips
Philips Electronics
Description : DUAL JK FLIP-FLOP WITH SET AND reSET; POSITIVE-EDGE TRIGGER

GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices AND are pin compatible WITH low power Schottky TTL (LSTTL). They are specified in compliance WITH JEDEC stANDard no. 7A.
The 74HC/HCT109 are DUAL POSITIVE-EDGE TRIGGERed, JK FLIP-FLOPs WITH indiviDUAL J, K inputs, clock (CP) inputs, SET (SD) AND reSET (RD) inputs; also complementary Q AND Q outputs.
The SET AND reSET are asynchronous active LOW inputs AND operate independently of the clock input.
The J AND K inputs control the state changes of the FLIP-FLOPs as described in the mode select function table.
The J AND K inputs must be stable one SET-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The JK design allows operation as a D-type FLIP-FLOP by tying the J AND K inputs together.
Schmitt-TRIGGER action in the clock input makes the circuit highly tolerant to slower clock rise AND fall times.

FEATURES
• J, K inputs for easy D-type FLIP-FLOP
• Toggle FLIP-FLOP or “do nothing” mode
• Output capability: stANDard
• ICC category: FLIP-FLOPs

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Part Name(s) : 74ALS109A 74ALS109AN 74ALS109AD Philips
Philips Electronics
Description : DUAL J-K positive edge-TRIGGERed FLIP-FLOP ith SET AND reSET

DESCRIPTION
The 74ALS109A is a DUAL positive edge-TRIGGERed JK-type FLIP-FLOP featuring indiviDUAL J, K, clock, SET, AND reSET inputs; also true AND complementary outputs. SET (SD) AND reSET (RD) are asynchronous active-Low inputs AND operate independently of the clock (CP) input.
The J AND K are edge-TRIGGERed inputs which control the state changes of the FLIP-FLOPs as described in the function table. Clock TRIGGERing occurs at a voltage level AND is not directly related to the transition time of the positive-going pulse. The J AND K inputs must be stable just one SETup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D FLIP-FLOP by tying J AND K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V AND 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

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Part Name(s) : SN54LS109AJ SN74LS109A SN74LS109AD SN74LS109AN Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise ANDfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J AND Kpins together.

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Part Name(s) : DV74AC109 DV74ACT109 DV74AC109D DV74ACT109D DV74AC109N DV74ACT109N AVG
AVG Semiconductors=>HITEK
Description : DUAL JK Positive Edge-TRIGGERed FLIP-FLOP

DUAL JK Positive Edge-TRIGGERed FLIP-FLOP

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Part Name(s) : 74HC109D 74HC109DB 74HC109N 74HC109PW 74HC109U 74HCMOS109 74HCT109D 74HCT109DB 74HCT109N 74HCT109PW 74HCT109U 74HCU109 Philips
Philips Electronics
Description : DUAL JK FLIP-FLOP WITH SET AND reSET; POSITIVE-EDGE TRIGGER

GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices AND are pin compatible WITH low power Schottky TTL (LSTTL). They are specified in compliance WITH JEDEC stANDard no. 7A.

FEATURES
• J,K inputs for easy D-type FLIP-FLOP
• Toggle FLIP-FLOP or “do nothing” mode
• Output capability: stANDard
• ICCcategory: FLIP-FLOPs

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Part Name(s) : SN54LS109A SN54LS109J SN74LS109 SN74LS109D SN74LS109N Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JKFLIP-FLOPs. The clocking operation is independent of rise ANDfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J AND Kpins together.

 

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Part Name(s) : 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV107PWDH Philips
Philips Electronics
Description : DUAL JK FLIP-FLOP WITH reSET; negative-edge TRIGGER

DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin AND function compatible WITH 74HC/HCT107.
The 74LV107 is a DUAL negative-edge TRIGGERed JK-type FLIP-FLOP featuring indiviDUAL J, K, clock (nCP) AND reSET (nR) inputs; also complementary Q AND Q outputs.
The J AND K inputs must be stable one SET-up time prior to the HIGH-to-LOW clock transition for predictable operation.
The reSET (nR) is an asynchronous active LOW input. When LOW, it overrides the clock AND data inputs, forcing the Q output LOW AND the Q output HIGH.
Schmitt-TRIGGER action in the clock input makes the circuit highly tolerant to slower clock rise AND fall times.

FEATURES
• Wide operating: 1.0 to 5.5 V
• Optimized for low voltage applications: 1.0 to 3.6 V
• Accepts TTL input levels between VCC = 2.7 V AND VCC = 3.6 V
• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25°C
• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C
• Output capability: stANDard
• ICC category: FLIP-FLOPs

 

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Part Name(s) : 74HC107 74HCT107 74HC107D 74HCT107D 74HC107DB 74HC107PW NXP
NXP Semiconductors.
Description : DUAL JK FLIP-FLOP WITH reSET; negative-edge TRIGGER

General description
The 74HC107; 74HCT107 is a DUAL negative edge TRIGGERed JK FLIP-FLOP featuring indiviDUAL J AND K inputs, clock (CP) AND reSET (R) inputs AND complementary Q AND Q outputs. The reSET is an asynchronous active LOW input AND operates independently of the clock input. The J AND K inputs control the state changes of the FLIP-FLOPs as described in the mode select function table. The J AND K inputs must be stable one SET-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
   
Features AND benefits
■ Complies WITH JEDEC stANDard no. 7A
■ Input levels:
    ◆ The 74HC107: CMOS levels
    ◆ The 74HCT107: TTL levels
■ ESD protection:
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from -40°C to +85°C AND from -40°C to +125°C
   

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Part Name(s) : MC74AC113 MC74ACT113 MC74AC113N MC74ACT113N MC74AC113D MC74ACT113D Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK Negative Edge-TRIGGERed FLIP-FLOP

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise AND fall times of the clock waveform. The JK design allows operation as a D FLIP-FLOP (refer to MC74AC74/74ACT74 data sheet) by connecting the J AND K inputs together.

Asynchronous Inputs:
   LOW input to SD (SET) SETs Q to HIGH level
   SET is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

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Part Name(s) : 5962-9070101MEA CD54HC109 CD54HCT109 CD74HC109 CD74HC109E CD74HC109EE4 CD74HC109M CD74HC109M96 CD74HC109M96E4 CD74HC109ME4 CD74HC109MG4 CD74HC109MT CD74HCT109 CD74HCT109E CD74HCT109EE4 CD74HCT109M CD74HCT109M96 CD74HCT109MG4 CD74HCT109MT HC109M HCT109M CD54HCT109F3A 8415001EA CD54HC109F3A Texas-Instruments
Texas Instruments
Description : DUAL J-K FLIP-FLOP WITH SET AND ReSET POSITIVE-EDGE TRIGGER

Description
The ’HC109 AND ’HCT109 are DUAL J-K FLIP-FLOPs WITH SET AND reSET. The FLIP-FLOP changes state WITH the positive transition of Clock (1CP AND 2CP).
The FLIP-FLOP is SET AND reSET by active-low S AND R, respectively. A low on both the SET AND reSET inputs simultaneously will force both Q AND Q outputs high. However, both SET AND reSET going high simultaneously results in an unpredictable output condition.

Features
• Asynchronous SET AND ReSET
• Schmitt TRIGGER Clock Inputs
• Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,
   TA = 25°C
• Fanout (Over Temperature Range)
   - StANDard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55°C to 125°C
• Balanced Propagation Delay AND Transition Times
• Significant Power Reduction Compared to LSTTL
   Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
      at VCC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility,
      VIL= 0.8V (Max), VIH = 2V (Min)
   - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

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