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Part Name(s) : SN54LS109AJ SN74LS109A SN74LS109AD SN74LS109AN Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J and Kpins together.

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Part Name(s) : DV74AC109 DV74ACT109 DV74AC109D DV74ACT109D DV74AC109N DV74ACT109N AVG
AVG Semiconductors=>HITEK
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

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Part Name(s) : SN54LS109A SN54LS109J SN74LS109 SN74LS109D SN74LS109N Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JKFLIP-FLOPs. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J and Kpins together.

 

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Part Name(s) : DV74AC112 DV74AC112N DV74AC112D AVG
AVG Semiconductors=>HITEK
Description : DUAL JK Negative EDGE-TRIGGERED FLIP-FLOP

DUAL JK Negative EDGE-TRIGGERED FLIP-FLOP

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Part Name(s) : SN54LS107A SN54LS107AJ SN74LS107A SN74LS107AD SN74LS107AN Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS107A is a DUAL JK FLIP-FLOP with indiviDUAL J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 /74LS107A is the same as the SN54/74LS73A but has corner power pins.

 

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Part Name(s) : MC74AC113 MC74ACT113 MC74AC113N MC74ACT113N MC74AC113D MC74ACT113D Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK Negative EDGE-TRIGGERED FLIP-FLOP

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D FLIP-FLOP (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

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Part Name(s) : 74ALS109A 74ALS109AN 74ALS109AD Philips
Philips Electronics
Description : DUAL J-K POSITIVE EDGE-TRIGGERED FLIP-FLOP ith set and reset

DESCRIPTION
The 74ALS109A is a DUAL POSITIVE EDGE-TRIGGERED JK-type FLIP-FLOP featuring indiviDUAL J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input.
The J and K are EDGE-TRIGGERED inputs which control the state changes of the FLIP-FLOPs as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the POSITIVE-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D FLIP-FLOP by tying J and K inputs together. Although the clock input is level sensitive, the POSITIVE transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

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Part Name(s) : SN54LS74AJ SN74LS74A SN74LS74AD SN74LS74AN SN54LS74A Motorola
Motorola => Freescale
Description : DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS74A DUAL EDGE-TRIGGERED FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-type FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL clear and set inputs, and also complementary Q and Q outputs.
Information at input D is transferred to the Q output on the POSITIVE-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the POSITIVE-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

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Part Name(s) : 74F50728 I74F50728D I74F50728N N74F50728D N74F50728N Philips
Philips Electronics
Description : Synchronizing cascaded DUAL POSITIVE EDGE-TRIGGERED D-type FLIP-FLOP

DESCRIPTION
The 74F50728 is a cascaded DUAL POSITIVE edge–triggered D–type featuring indiviDUAL data, clock, set and reset inputs; also true and complementary outputs.

FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• See 74F5074 for synchronizing DUAL D-type FLIP-FLOP
• See 74F50109 for synchronizing DUAL J–K POSITIVE EDGE-TRIGGERED FLIP-FLOP
• See 74F50729 for synchronizing DUAL DUAL D-type FLIP-FLOP with EDGE-TRIGGERED set and reset
• Industrial temperature range available (–40°C to +85°C)

 

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Part Name(s) : MC74AC112 MC74AC112D MC74AC112N MC74ACT112 MC74ACT112D MC74ACT112N ON1165 Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK Negative EDGE-TRIGGERED FLIP-FLOP

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D FLIP-FLOP (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   LOW input to CD (Clear) sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT112 Has TTL Compatible Inputs

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