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Part Name(s) : HEF4015B HEF4015BD HEF4015BDF HEF4015BF HEF4015BN HEF4015BP HEF4015BPN HEF4015BT HEF4015BTD HEF4015BDB HEF4015BU HEF4015BPB Philips
Philips Electronics
Description : DUAL 4-BIT STATIC SHIFT REGISTER

DESCRIPTION
The HEF4015B is a DUAL edge-triggered 4-BIT STATIC SHIFT REGISTER (serial-to-parallel converter). Each SHIFT REGISTER has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0to O3) and an overriding synchronous master reset input (MR).

APPLICATION INFORMATION
Some examples of applications for the HEF4015B are:
• Serial-to-parallel converter
• Buffer stores
• General purpose REGISTER

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Part Name(s) : MC14517 MC14517B MC14517BCP MC14517BCL MC14517BDW Motorola
Motorola => Freescale
Description : DUAL 64-BIT STATIC SHIFT REGISTER

The MC14517B DUAL 64–bit STATIC SHIFT REGISTER consists of two identical, independent, 64–bit REGISTERs. Each REGISTER has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data input is entered by clocking, regardless of the state of the write enable input. An output is disabled (open circuited) when the write enable input is high. During this time, data appearing at the data input as well as the 16–bit, 32–bit, and 48–bit taps may be entered into the device by application of a clock pulse. This feature permits the REGISTER to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used. This device is useful in time delay circuits, temporary memory storage circuits, and other serial SHIFT REGISTER applications.

• Diode Protection on All Inputs
• Fully STATIC Operation
• Output Transitions Occur on the Rising Edge of the Clock Pulse
• Exceedingly Slow Input Transition Rates May Be Applied to the Clock Input
• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications
SHIFT REGISTERs of any Length may be Fully Loaded with 16 Clock Pulses
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range

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Part Name(s) : MC14562B MC14562BCP ONSEMI
ON Semiconductor
Description : 128-Bit STATIC SHIFT REGISTER

The MC14562B is a 128–bit STATIC SHIFT REGISTER constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the SHIFT REGISTER on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128. This complementary MOS SHIFT REGISTER is primarily used where low power dissipation and/or high noise immunity is desired.

• Diode Protection on All Inputs
• Fully STATIC Operation
• Cascadable to Provide Longer SHIFT REGISTER Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range

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Part Name(s) : MC14562 MC14562B MC14562BCP ON-Semiconductor
ON Semiconductor
Description : 128-Bit STATIC SHIFT REGISTER

The MC14562B is a 128–bit STATIC SHIFT REGISTER constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the SHIFT REGISTER on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128. This complementary MOS SHIFT REGISTER is primarily used where low power dissipation and/or high noise immunity is desired.

•Diode Protection on All Inputs
•Fully STATIC Operation
•Cascadable to Provide Longer SHIFT REGISTER Lengths
•Supply Voltage Range = 3.0Vdc to 18Vdc
•Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range

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Part Name(s) : MC14562B MC14562BCL MC14562BCP MC14562BD Motorola
Motorola => Freescale
Description : 128–bit STATIC SHIFT REGISTER

TheMC14562B is a 128–bit STATIC SHIFT REGISTER constructed with MOS P–channeland N–channel enhancement mode devices in a single monolithicstructure. Data is clockedin and out of the SHIFT REGISTER on the positiveedge of the clock input. Data outputs are availableevery 16 bits, from 16 through bit 128. This complementary MOS SHIFT REGISTER is primarily used where low power dissipation and/or high noise immunity is desired.

• Diode Protection on All Inputs
• Fully STATIC Operation
• Cascadable to Provide Longer SHIFT REGISTER Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range

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Part Name(s) : HD14021B Hitachi
Hitachi -> Renesas Electronics
Description : 8-bit STATIC SHIFT REGISTER

8-bit STATIC SHIFT REGISTER

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Part Name(s) : HD14014B Hitachi
Hitachi -> Renesas Electronics
Description : 8-bit STATIC SHIFT REGISTER

8-bit STATIC SHIFT REGISTER

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Part Name(s) : HEF4517B HEF4517BD HEF4517BDF HEF4517BF HEF4517BN HEF4517BP HEF4517BPB HEF4517BPN HEF4517BT HEF4517BTD HEF4517BU Philips
Philips Electronics
Description : DUAL 64-BIT STATIC SHIFT REGISTER

DESCRIPTION
The HEF4517B consists of two identical, independent 64-BIT STATIC SHIFT REGISTERs. Each REGISTER has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock, regardless of the state of PE/EO.
When PE/EO is LOW the outputs are enabled and the device is in the 64-BIT serial mode.

When PE/EO is HIGH the outputs are disabled (high impedance OFF-state), the 64-BIT SHIFT REGISTER is divided into four 16-bit SHIFT REGISTERs with D, O16, O32 and O48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

 

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Part Name(s) : HEF4015B HEF4015BP HEF4015BT HEF4015BT,653 HEF4015BT,652 NXP
NXP Semiconductors.
Description : DUAL 4-BIT STATIC SHIFT REGISTER

General description
The HEF4015B is a DUAL edge-triggered 4-BIT STATIC SHIFT REGISTER (serial-to-parallel converter). Each SHIFT REGISTER has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Information present on D is SHIFTed to the first REGISTER position, and all the data in the REGISTER is SHIFTed one position to the right on the LOW-to-HIGH transition of CP. A HIGH on MR clears the REGISTER and forces Q0 to Q3 to LOW, independent of CP and D. The clock input’s Schmitt trigger action makes the input highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input.

Features and benefits
■ Tolerant of slow clock rise and fall times
■ Fully STATIC operation
■ 5 V, 10 V, and 15 V parametric ratings
■ Standardized symmetrical output characteristics
■ Specified from -40 °C to +85 °C.
■ Complies with JEDEC standard JESD 13-B

Applications
■ Serial-to-parallel converter
■ Buffer stores
■ General purpose REGISTER

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Part Name(s) : MC14015B MC14015BCL MC14015BCP MC14015BD Motorola
Motorola => Freescale
Description : DUAL 4-BIT STATIC SHIFT REGISTER

The MC14015B DUAL 4–bit STATIC SHIFT REGISTER is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output REGISTERs. Each REGISTER has independent Clock and Reset inputs with a single serial Data input. The REGISTER states are type D master–slave flip–flops. Data is SHIFTed from one stage to the next during the positive–going clock transition. Each REGISTER can be cleared when a high level is applied on the Reset line. These complementary MOS SHIFT REGISTERs find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired.

• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design —
   Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse.
• Capable of Driving Two Low–power TTL Loads or One Low–power
   Schottky TTL Load Over the Rated Temperature Range.

 

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