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Part Name(s) : 54LS137 74LS137 SN54LS137 SN54LS137J SN74LS137 SN74LS137D SN74LS137N Motorola
Motorola => Freescale
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY

 

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Part Name(s) : SN54ALS137AFK SN54ALS137AJ TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

description
The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line DECODERS/DEMULTIPLEXERS with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as DECODERS/DEMULTIPLEXERS. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls (G1 and G2) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

• Combines Decoder and 3-Bit Address Latch
• Incorporates Two Output Enables to Simplify Cascading
• Package Options Include Plastic Small Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

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Part Name(s) : DM54LS138N National-Semiconductor
National ->Texas Instruments
Description : DECODERS/DEMULTIPLEXERS

General Description
These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay intro duced by the decoder is negligible.

Features
■ Designed specifically for high speed:
   Memory decoders
   Data transmission systems
■ LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception
■ LS139 contains two fully independent 2-to-4-line DECODERS/DEMULTIPLEXERS
■ Schottky clamped for high performance
■ Typical propagation delay (3 levels of logic)
   LS138 21 ns
   LS139 21 ns
■ Typical power dissipation
   LS138 32 mW
   LS139 34 mW
■ Alternate Military/Aerospace devices (54LS138, 54LS139) are available. Contact a National Semicon ductor Sales Office/Distributor for specifications.

 

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Part Name(s) : SN74LS138DE4 SN74LS138NSRE4 SN74S138ADE4 SN74S138ANSR SN74S138ANSRE4 SN74S138N TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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Part Name(s) : 74LS137 SN54LS137 SN54LS137FK SN54LS137J SN54LS137W SN74LS137 SN74LS137D SN74LS137DR SN74LS137J SN74LS137N SN74LS137N3 SNJ54LS137FK SNJ54LS137J SNJ54LS137W TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

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Part Name(s) : AC139M CD54AC139 CD54AC139F3A CD74AC139 CD74AC139E CD74AC139M CD74AC139M96 TI
Texas Instruments
Description : DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

description/ordering information
The ’AC139 devices are dual 2-line to 4-line DECODERS/DEMULTIPLEXERS designed for 1.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G) input can be used as a data line in demultiplexing applications. These DECODERS/DEMULTIPLEXERS feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

● AC Types Feature 1.5-V to 5.5-V Operation
   and Balanced Noise Immunity at 30% of the
   Supply Voltage
● Buffered Inputs
● Incorporate Two Enable Inputs to Simplify
   Cascading and/or Data Reception
● Speed of Bipolar F, AS, and S, With
   Significantly Reduced Power Consumption
● Balanced Propagation Delays
● ±24-mA Output Drive Current
   – Fanout to 15 F Devices
● SCR-Latchup-Resistant CMOS Process and
   Circuit Design
● Exceeds 2-kV ESD Protection Per
   MIL-STD-883, Method 3015

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Part Name(s) : CD54AC139 CD74AC139 CD74AC139EE4 CD74AC139M CD74AC139M96 CD74AC139MG4 CD54AC139F3A CD74AC139E AC139M Texas-Instruments
Texas Instruments
Description : DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

description/ordering information
The ’AC139 devices are dual 2-line to 4-line DECODERS/DEMULTIPLEXERS designed for 1.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G) input can be used as a data line in demultiplexing applications. These DECODERS/DEMULTIPLEXERS feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

● AC Types Feature 1.5-V to 5.5-V Operation
   and Balanced Noise Immunity at 30% of the
   Supply Voltage
● Buffered Inputs
● Incorporate Two Enable Inputs to Simplify
   Cascading and/or Data Reception
● Speed of Bipolar F, AS, and S, With
   Significantly Reduced Power Consumption
● Balanced Propagation Delays
● ±24-mA Output Drive Current
   – Fanout to 15 F Devices
● SCR-Latchup-Resistant CMOS Process and
   Circuit Design
● Exceeds 2-kV ESD Protection Per
   MIL-STD-883, Method 3015

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Part Name(s) : SN54AHCT138FK SN54AHCT138J SN54AHCT138W SN74AHCT138DB SN74AHCT138DGV SN74AHCT138NS SN74AHCT138RGY TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

description/ordering information
The ’AHCT139 devices are dual 2-line to 4-line DECODERS/DEMULTIPLEXERS designed for 4.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

● Inputs Are TTL-Voltage Compatible
● Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
● Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
● Latch-Up Performance Exceeds 250 mA Per JESD 17
● ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 200-V Machine Model (A115-A)
   – 1000-V Charged-Device Model (C101)

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Part Name(s) : 5962-9066501M2A 5962-9066501MEA 5962-9066501MFA SN54ALS137A SN74ALS137A SN74ALS137AD SN74ALS137ADE4 SN74ALS137ADG4 SN74ALS137ANE4 SN74AS137 SN74AS137D SN74AS137DR SN74AS137N SNJ54ALS137AFK SNJ54ALS137AJ SNJ54ALS137AW ALS137A SN74ALS137AN Texas-Instruments
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

description
The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line DECODERS/DEMULTIPLEXERS with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as DECODERS/DEMULTIPLEXERS. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls (G1 and G2) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

• Combines Decoder and 3-Bit Address Latch
• Incorporates Two Output Enables to Simplify Cascading
• Package Options Include Plastic Small Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

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Part Name(s) : SN54ALS137A SN74ALS137A SN74AS137 5962-9066501M2A 5962-9066501MEA 5962-9066501MFA SN74ALS137AD SN74ALS137ADE4 SN74ALS137ADR SN74ALS137ADRE4 SN74ALS137AN SN74ALS137ANE4 SN74ALS137ANSR SN74ALS137ANSRE4 SN74AS137D SN74AS137DR SN74AS137N SNJ54ALS137AFK SNJ54ALS137AJ SNJ54ALS137AW TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

description
The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line DECODERS/DEMULTIPLEXERS with latches on the three address inputs. When the latch-enable (LE) input is low, the devices act as DECODERS/DEMULTIPLEXERS. When LE goes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls (G1 and G2) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems.

• Combines Decoder and 3-Bit Address Latch
• Incorporates Two Output Enables to Simplify Cascading
• Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

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