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Part Name(s) : TVP5150A TVP5150AM1 TVP5150AM1PBS TVP5150AM1PBSR TVP5150AM1ZQC TVP5150AM1ZQCR TVP5150APBS TVP5150APBSR TVP5150AZQC TVP5150AZQCR TI
Texas Instruments
Description : Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector

Introduction
The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150A decoder can be programmed using an I2C serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.
The TVP5150A decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The TVP5150A decoder includes one 9-bit analog-to-digital converter (ADC) with 2x sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.
The TVP5150A decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders.
Complementary 4-line adaptive comb filtering is available for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts; a chroma trap filter is also available.

Features
• Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video data
• Supports ITU-R BT.601 standard sampling
• High-speed 9-bit ADC
• Two composite inputs or one S-video input
• Fully differential CMOS analog preprocessing channels with clamping and automatic
   gain control (AGC) for best signal-to-noise (S/N) performance
• Ultralow power consumption: 115 mW typical
• 32-pin TQFP package
• Power-down mode: <1 mW
• Brightness, contrast, saturation, hue, and sharpness control through I2C
• Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and cross-
   chrominance noise reduction
• Patented architecture for locking to weak, noisy, or unstable signals
• Single 14.31818-MHz crystal for all standards
• Internal phase-locked loop (PLL) for line-locked clock and sampling
• Subcarrier Genlock output for synchronizing color subcarrier of external encoder
• Standard programmable video output format:
   − ITU-R BT.656, 8-bit 4:2:2 with embedded syncs
   − 8-bit 4:2:2 with discrete syncs
• Macrovision™ copy protection detection
• Advanced programmable video output formats:
   − 2x oversampled raw VBI data during active video
   − Sliced VBI data during horizontal blanking or active video
• VBI modes supported
   − Teletext (NABTS, WST)
   − Closed-caption decode with FIFO, and extended data services (EDS)
   − Wide screen signaling, video program system, CGMS, vertical interval time code
   − Gemstar 1x/2x electronic program guide compatible mode
   − Custom configuration mode that allows the user to program the slice engine for unique
      VBI data signals
• Power-on reset

Part Name(s) : TVP5150APBS TVP5150APBSR TVP5150AZQC TVP5150AZQCR TI
Texas Instruments
Description : Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector

Introduction
The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150A decoder can be programmed using an I2C serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.
The TVP5150A decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The TVP5150A decoder includes one 9-bit analog-to-digital converter (ADC) with 2x sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.

Features
• Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M, N),
   and SECAM (B, D, G, K, K1, L) video data
• Supports ITU-R BT.601 standard sampling
• High-speed 9-bit ADC
• Two composite inputs or one S-video input
• Fully differential CMOS analog preprocessing channels with clamping and automatic
   gain control (AGC) for best signal-to-noise (S/N) performance
• Ultralow power consumption: 115 mW typical
• 32-pin TQFP package
• Power-down mode: <1 mW
• Brightness, contrast, saturation, hue, and sharpness control through I2C
• Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and
   cross-chrominance noise reduction
• Patented architecture for locking to weak, noisy, or unstable signals
• Single 14.31818-MHz crystal for all standards
• Internal phase-locked loop (PLL) for line-locked clock and sampling
• Subcarrier Genlock output for synchronizing color subcarrier of external encoder
• Standard programmable video output format:
   − ITU-R BT.656, 8-bit 4:2:2 with embedded syncs
   − 8-bit 4:2:2 with discrete syncs
• Macrovision™ copy protection detection
• Advanced programmable video output formats:
   − 2x oversampled raw VBI data during active video
   − Sliced VBI data during horizontal blanking or active video
• VBI modes supported
   − Teletext (NABTS, WST)
   − Closed-caption decode with FIFO, and extended data services (EDS)
   − Wide screen signaling, video program system, CGMS, vertical interval tme code
   − Gemstar 1x/2x electronic program guide compatible mode
   − Custom configuration mode that allows the user to program the slice engine for unique
      VBI data signals
• Power-on reset

Applications
The following is a partial list of suggested applications:
• Digital television
• PDA
• Notebook PCs
• Cell phones
• Video recorder/players
• Internet appliances/web pads
• Handheld games

Part Name(s) : SAA7112 SAA7112H/01 Philips
Philips Electronics
Description : Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN)

GENERAL DESCRIPTION
The PELICAN SAA7112 is a video capture device for applications at the image port of VGA controllers.
The SAA7112 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder and a SAA7140B based scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit (see Fig.1).

FEATURES
The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights:
Video Decoder
• Six analog inputs, internal analog source selectors, (e.g. 6 × CVBS or(2 × YC and 2 × CVBS) or (1 × YC and 4 × CVBS)
• Two analog preprocessing channels, including built in analog anti-alias filters
• Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel
• Two 8 bit video CMOS Analog-to-Digital Converters (ADCs)
• Automatic Clamp Control (ACC) for CVBS, Y and C
• Switchable white peak control
• On-chip line locked clock generation in accordance with CCIR-601
• Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR
• Requires only one crystal (32.11 MHz) for all standards
• Horizontal and vertical sync detection
• Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC
• Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM
• User programmable luminance peaking or aperture correction
• Cross-colour reduction for NTSC by chrominance combination filtering
• PAL delay line for correcting PAL phase errors
• Real time status information output (RTCO)
• Independent Brightness Contrast Saturation (BCS) adjustment for decoder part.

Video Scaler
• Horizontal and vertical down-scaling and up-scaling to randomly sized windows
• Horizontal and vertical scaling range: 2 (zoom) to 1⁄64 (icon); vertical zoom might be restricted
• Anti-alias- and accumulating filter for horizontal scaling
• Vertical scaling with linear phase interpolation (6-bit phase accuracy) and accumulating filter for anti-aliasing
• Horizontal phase correct up- and down-scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy
• Two independent programming sets for scaler part, to define two ‘ranges’ per field or per frame
• Field-wise switching between decoder-part and expansion port input
• Brightness, contrast and saturation controls for scaled outputs.

VBI-data decoder and text slicer
• versatile VBI-data decoder, slicer, clock regeneration and byte synchronization; e.g. for WST, NABST, Close Caption, WSS, etc.

Audio clock generation
• Generation of a field locked audio master clock to support a constant number of audio clocks per video field
• Generation of an audio serial and left/right (channel) clock signal.

Digital I/O interfaces
• Real time signal port (R-port), including continuous line locked reference clock and real time status information
• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV
   – output from decoder part, real time, or
   – input to scaler part, e.g. video from MPEG-decoder
• Video image port (I-port) configurable for 8-bit (16-bit) data in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals
• 8-bit data Host port (H-port) for 16-bit extension of I-port
• Discontinuous data streams supported
• 32-word × 4 bytes FIFO register for video output data
• 16-word × 4 bytes FIFO register for decoded VBI output data Scaled 4 : 2 : 2, 4 : 1 : 1 YUV output
• Scaled 8-bit luminance only and raw data output
• Decoded VBI data output.

 

Part Name(s) : SAF7118 SAF7118EH SAF7118H Philips
Philips Electronics
Description : Multistandard video decoder with adaptive comb filter and component video input

GENERAL DESCRIPTION
The SAF7118 is a video capture device for applications at the image port of VGA controllers. Philips X-VIP is a new multistandard comb filter video decoder chip with additional component processing, providing high quality, optionally scaled, video.
The SAF7118 is a combination of a four-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC with succeeding decimation filters from 27 to 13.5 MHz data rate. Each preprocessing channel comes with an automatic clamp and gain control.
The SAF7118 combines a Clock Generation Circuit (CGC), a digital multistandard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and downscaling and a brightness, contrast and saturation control circuit.

FEATURES
Video acquisition/clock
• Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be used to convert e.g. Vestigial Side Band (VSB) signals)
• Up to eight analog Y + C inputs, split as desired
• Up to four analog component inputs, with embedded or separate sync, split as desired
• Four on-chip anti-aliasing filters in front of the Analog-to-Digital Converters (ADCs)
• Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
• Switchable white peak control
• Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
• Fully programmable static gain or Automatic Gain Control (AGC), matching to the particular signal properties
• On-chip line-locked clock generation in accordance with “ITU 601”
• Requires only one crystal (32.11 or 24.576 MHz) for all standards
• Horizontal and vertical sync detection.

Video decoder
• Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
• Automatic detection of any supported colour standard
• Luminance and chrominance signal processing for PAL B, G, D, H, I and N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
• Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation, also with VTR signals
   – Increased luminance and chrominance bandwidth for all PAL and NTSC standards
   – Reduced cross colour and cross luminance artefacts
• PAL delay line for correcting PAL phase errors
• Brightness Contrast Saturation (BCS) adjustment, separately for composite and baseband signals
• User programmable sharpness control
• Detection of copy-protected signals according to the Macrovision(1) standard, indicating level of protection
• Independent gain and offset adjustment for raw data path.

Component video processing
• RGB component inputs
• Y-PB-PR component inputs
• Fast blanking between CVBS and synchronous component inputs
• Digital RGB to Y-CB-CR matrix.

Video scaler
• Horizontal and vertical downscaling and upscaling to randomly sized windows
• Horizontal and vertical scaling range: variable zoom to 1⁄64 (icon) (it should be noted that the H and V zoom are restricted by the transfer data rates)
• Anti-alias and accumulating filter for horizontal scaling
• Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
• Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
• Two independent programming sets for scaler part, to define two ‘ranges’ per field or sequences over frames
• Fieldwise switching between decoder part and expansion port (X port) input
• Brightness, contrast and saturation controls for scaled outputs.

Vertical Blanking Interval (VBI) data decoder and slicer
• Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), etc.

Audio clock generation
• Generation of a field-locked audio master clock to support a constant number of audio clocks per video field
• Generation of an audio serial and left/right (channel) clock signal.

Digital I/O interfaces
• Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to document “RTC Functional Specification” for details)
• Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-CB-CR:
   – Output from decoder part, real-time and unscaled
   – Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
• Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and handshake signals
• Discontinuous data streams supported
• 32-word × 4-byte FIFO register for video output data
• 28-word × 4-byte FIFO register for decoded VBI data output
• Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-CB-CR output
• Scaled 8-bit luminance only and raw CVBS data output
• Sliced, decoded VBI data output.

Miscellaneous
• Power-on control
• 5 V tolerant digital inputs and I/O ports
• Software controlled power saving standby modes supported
• Programming via serial I2C-bus, full read back ability by an external controller, bit rate up to 400 kbit/s
• Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994”.

APPLICATIONS
• PC-video capture and editing
• Personal video recorders (time shifting)
• Cable, terrestrial, and satellite set-top boxes
• Internet terminals
• Flat-panel monitors
• DVD recordable players
• AV-ready hard-disk drivers
• Digital televisions/scan conversion
• Video surveillance/security
• Video editing/post production
• Video phones
• Video projectors
• Digital VCRs.

 

Part Name(s) : HCTL-2032 HCTL-2032-SC HCTL-2032-SCT HCTL-2022 AVAGO
Avago Technologies
Description : Quadrature Decoder/ Counter Interface ICs

Description
The HCTL-20XX-XX is CMOS ICs that perform the quadrature decoder, counter, and bus interface function. The HCTL-20XX-XX is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-20XX-XX consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise flters allows reliable operation in noisy environments. The HCTL-20XX-XX contains 32-bit counter and provides LSTLL compatible tri-state output buffers. Operation is specifed for a temperature range from -40 to +100°C at clock frequencies up to 33MHz.
The HCTL-2032 and HCTL-2032-SC have dual-axis capability and index channel support. Both devices can be programmed as 4x/2x/1x count mode. The HCTL-2032 and HCTL2032-SC also provides quadrature decoder output signals and cascade signals for use with many standard computer ICs.
The HCTL-2022 has most of the HCTL-2032 features, but it can only supports single axis and fxed at 4x count mode. The HCTL-2022 doesn’t provide decoder output and cascade signals.

Features
• Interfaces Encoder to Microprocessor
• 33 MHz Clock Operation
• Programmable Count Modes (1x, 2x or 4x)
• Single or Dual Axis Support
• Index Channel Support
• High Noise Immunity:
• Schmitt Trigger Inputs and Digital Noise Filter
• 32-Bit Binary Up/Down Counter
• Latched Outputs
• 8-Bit Tristate Interface
• 8, 16, 24, or 32-Bit Operating Modes
• Quadrature Decoder Output Signals, Up/Down and Count
• Cascade Output Signals, Up/Down and Count
• Substantially Reduced System Software
• 5V Operation (VDD - VSS)
• TTL/CMOS Compatible I/O
• Operating Temperature: -40°C to 100°C
• 32-Pin PDIP, 32-Pin SOIC, 20-Pin PDIP

Applications
• Interface Quadrature Incremental Encoders to Microprocessors
• Interface Digital Potentiometers to Digital Data Input Buses

 

Part Name(s) : L138AQ1 SN74LVC138A-Q1 CLVC138AQPWRG4Q1 SN74LVC138AQDRG4Q1 SN74LVC138AQDRQ1 SN74LVC138AQPWRQ1 TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

DESCRIPTION/ORDERING INFORMATION
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

FEATURES
• Qualified for Automotive Applications
• ESD Protection Exceeds 2000 V Per
   MIL-STD-883, Method 3015; Exceeds 200 V
   Using Machine Model (C = 200 pF, R = 0)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V
   at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V
   at VCC = 3.3 V, TA = 25°C

Part Name(s) : PQFP208 STI5500 ST-Microelectronics
STMicroelectronics
Description : SET TOP BOX / DVD BACKEND DECODER WITH INTEGRATED HOST PROCESSOR

DESCRIPTION
The STi5500 is the first of a new generation of integrated multimedia decoder engines for set top
box and DVD applications. It offers a high level of integration by reducing the complete set top box decoding chain from Transport Demux to PAL/NTSC Encoder onto one chip. At the same time
it dramatically enhances CPU and Graphics per formance, and cuts down total system memory cost.

.ENHANCED 32-BIT VL-RISC CPU
- FAST INTEGER/BIT OPERATION AND VERY HIGH CODE DENSITY
.HIGH  PERFORMANCE  MEMORY/CACHE SUBSYSTEM
- 2KBYTES INSTRUCTION CACHE, 2KBYTES SRAM, 2KBYTES DATA CACHE/SRAM
- 160MBYTES/S BANDWIDTH
.COMBINED VIDEO AND AUDIO DECODER CORE
- VIDEO DECODER FULLY SUPPORTS MPEG-2 MP@ML
- MEMORY REDUCTION - PAL MP@ML IN 12MBITS
- 2 TO 8 BIT PER PIXEL OSD OPTIONS
- LETTERBOX (16:9) DISPLAY FORMAT
- HORIZONTAL AND VERTICAL RESIZING FUNCTIONS
- AUDIO DECODER SUPPORTS LAYERS 1 AND 2 OF MPEG, INTERFACE TO EXTERNAL DOLBY AC-3 DECODER
.PAL/NTSC ENCODER
- MACROVISIONVERSION 7.01/6.1 COMPATIBLE
- TELETEXT, AND CLOSED CAPTION
- SIMULTANEOUS OUTPUT OF RGB, CVBS AND COMPONENT VIDEO
.HIGH PERFORMANCE SDRAM MEMORY INTERFACE
- SUPPORTS 1 OR 2 16MBIT 100MHz SDRAMS
- ACCESSIBLE BY MPEG DECODER, CPU AND DMAS
- HIGH BANDWIDTH ACCESS FROM CPU ALLOWS HIGH PERFORMANCE OSD OPERATIONS
.PROGRAMMABLE MEMORY INTERFACE
- 4 BANKS EACH 8/16 BITS WIDE
- SUPPORT FOR MIXED MEMORY, PERIPHERALS, DRAM AND POWER PC
.LINK INTERFACE
- SERIAL INPUT
- SUPPORTS DSS, DVB, AND DVD BITSTREAMS
- 32 PIDS SUPPORTED
- DES AND DVB DESCRAMBLERS
- 32 SI/PSI FILTERS OF 16 BYTES
.VECTORED INTERRUPTS - 8 PRIORITIZED LEVELS
.DMA ENGINES/INTERFACES
- 2 UARTS, 1 I2C CONTROLLER, 3 PWM OUTPUTS, 3 TIMERS, 3 CAPTURE TIMERS
- 24 BITS OF PIO SHARED WITH SERIAL INTERFACES
- OS LINK INTERFACE
- BLOCK MOVE DMA, 2 MPEG DMAS
- TELETEXT INTERFACE
.PROFESSIONAL TOOLSET SUPPORT
- ANSI C COMPILER AND LIBRARIES
- INQUEST ADVANCED DEBUGGING TOOLS
.NON-INTRUSIVE DEBUG CONTROLLER
- HARDWARE BREAKPOINTS
- REAL TIME TRACE
.208 PIN PQFP PACKAGE

Part Name(s) : TDA955X TDA955XN1 TDA955XPS TDA956X TDA956XN1 TDA956XPS TDA958X TDA958XN1 TDA958XPS Philips
Philips Electronics
Description : TV signal processor-Teletext decoder with embedded µ-Controller

GENERAL DESCRIPTION
The various versions of the TDA955X/6X/8X PS/N1 series combine the functions of a video processor together with a µ-Controller and US Closed Caption decoder. Several versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes.

FEATURES
TV-signal processor
• Multi-standard vision IF circuit with alignment-free PLL demodulator
• Internal (switchable) time-constant for the IF-AGC circuit
• A choice can be made between versions with mono intercarrier sound FM demodulator and versions with QSS IF amplifier. In the QSS versions without East-West output an AM/FM mode can be activated. In that case both the QSS amplifier (for AM demodulation) and the FM demodulator are available.
• The mono intercarrier sound circuit has a selective FM-PLL demodulator which can be switched to the different FM sound frequencies (4.5/5.5/6.0/6.5 MHz). The quality of this system is such that the external band-pass filters can be omitted.
• The FM-PLL demodulator can be set to centre frequencies of 4.74/5.74 MHz so that a second sound channel can be demodulated. In such an application it is necessary that an external bandpass filter is inserted.
• The QSS amplifier and mono intercarrier sound circuit of some versions can be used for the demodulation of FM radio signals
• Source selection between the ‘internal’ CVBS and one external CVBS or Y/C signal
• Integrated chrominance trap circuit
• Integrated luminance delay line with adjustable delay time
• Picture improvement features with peaking (with switchable centre frequency, depeaking, variable positive/negative overshoot ratio and video dependent coring) and blue- and black stretching
• Integrated chroma band-pass filter with switchable centre frequency
• Only one reference (12 MHz) crystal required for the µ-Controller, Teletext- and the colour decoder
• PAL/NTSC or multi-standard colour decoder with automatic search system
• Internal base-band delay line
• Indication of the Signal-to-Noise ratio of the incoming CVBS signal
• RGB control circuit with ‘Continuous Cathode Calibration’, white point and black level off-set adjustment so that the colour temperature of the dark and the light parts of the screen can be chosen independently.
• A linear RGB/YUV/YPBPR input with fast blanking for external RGB/YUV sources. The synchronisation circuit can be connected to the incoming Y signal. The Text/OSD signals are internally supplied from the µ-Controller/Teletext decoder.
• Contrast reduction possibility during mixed-mode of OSD and Text signals
• Adjustable ‘wide blanking’ of the RGB outputs
• Horizontal synchronization with two control loops and alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output stages
• Horizontal and vertical geometry processing
• Horizontal and vertical zoom function for 16 : 9 applications
• Horizontal parallelogram and bow correction for large screen picture tubes
• Low-power start-up of the horizontal drive circuit

 

Part Name(s) : SN74LVC138A-EP SN74LVC138AMPWTEP SN74LVC138AQDREP SN74LVC138AQPWREP V62/04657-01XE V62/04657-01YE V62/04657-02YE C138AEP C138AME TI
Texas Instruments
Description : 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

DESCRIPTION/ORDERING INFORMATION
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

FEATURES
• ESD Protection Exceeds 2000 V Per
   MIL-STD-883, Method 3015; Exceeds 200 V
   Using Machine Model (C = 200 pF, R = 0)
• Operates From 2 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.8 ns at 3.3 V
• Typical VOLP (Output Ground Bounce) < 0.8 V
   at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) > 2 V at
   VCC = 3.3 V, TA = 25°C

SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly/Test Site
• One Fabrication Site
• Available in Military (–55°C/125°C)
   Temperature Range(1)
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability

Part Name(s) : BCM7412 Broadcom
Broadcom Corporation
Description : AVC/VC-1/MPEG HIGH-DEFINITION DECODER

FUNCTIONAL COMPONENTS

• H.264/MPEG-4 part 10 decoder
• VC-1 Advanced, Simple, Main decoder
• MPEG-2 decoder
• Programmable audio decoder
• Transport demultiplexer
• Still Image Decoder (SID)
• HD-compatible digital video output port
• Multi-host control/status interface
• DDR SDRAM controller
 

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