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Part Name(s) : 74ALS74 Fairchild
Fairchild Semiconductor
Description : DUAL D POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR View

General Description
The DM74ALS74A contains two independent positive edge-triggered FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.
Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.
Asynchronous PRESET AND CLEAR inputs will set or CLEAR Q output respectively upon the application of low level signal.

Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process
■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart
■ Improved AC performance over LS74 at approximately half the power

 

Part Name(s) : DM74AS74 DM74AS74M DM74AS74MX DM74AS74N DM74AS74SJX Fairchild
Fairchild Semiconductor
Description : DUAL D-TYPE POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR View

General Description
The AS74 is a DUAL edge-triggered FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.

Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process
■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart
■ Improved AC performance over S74 at approximately half the power

Part Name(s) : DM74ALS74A DM74ALS74ACW DM74ALS74AM DM74ALS74AMX DM74ALS74AN DM74ALS74ASJ DM74ALS74ASJX DM74ALS74 Fairchild
Fairchild Semiconductor
Description : DUAL D POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR View

General Description
The DM74ALS74A contains two independent positive edge-triggered FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL D, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.
Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.
Asynchronous PRESET AND CLEAR inputs will set or CLEAR Q output respectively upon the application of low level signal.

Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL process
■ Functionally AND pin-for-pin compatible WITH Schottky AND LS TTL counterpart
■ Improved AC performance over LS74 at approximately half the power

Part Name(s) : DM74LS109A DM74LS109AM DM74LS109AMX DM74LS109AN DM74LS109 Fairchild
Fairchild Semiconductor
Description : DUAL POSITIVE-EDGE-TRIGGEred J-K FLIP-FLOP WITH PRESET, CLEAR, AND Complementary Outputs View

General Description
This device contains two independent POSITIVE-EDGE-TRIGGEred J-K FLIP-FLOPs WITH complementary outputs. The J AND K data is accepted by the FLIP-FLOP on the rising edge of the clock pulse. The triggering occurs at a voltage level AND is not directly related to the transition time of the rising edge of the clock. The data on the J AND K inputs may be changed while the clock is HIGH or LOW as long as setup AND hold times are not violated. A low logic level on the PRESET or CLEAR inputs will set or reset the outputs regard less of the logic levels of the other inputs.


Part Name(s) : DM74ALS109A DM74ALS109AMX DM74ALS109AN DM74ALS109AM DM74ALS109ANX Fairchild
Fairchild Semiconductor
Description : DUAL J-K POSITIVE-EDGE-TRIGGEred FLIP-FLOP WITH PRESET AND CLEAR View

General Description
The DM74ALS109A is a DUAL edge-triggered FLIP-FLOP. Each FLIP-FLOP has indiviDUAL J, K, clock, CLEAR AND PRESET inputs, AND also complementary Q AND Q outputs.
   
Features
■ Switching specifications at 50 pF
■ Switching specifications guaranteed over full
    temperature AND VCC range
■ Advanced oxide-isolated, ion-implanted Schottky TTL
    process
■ Functionally AND pin for pin compatible WITH Schottky
    AND LS TTL counterpart
■ Improved AC performance over LS109 at approximately
    half the power
   

Part Name(s) : SN54LS74AJ SN74LS74A SN74LS74AD SN74LS74AN SN54LS74A Motorola
Motorola => Freescale
Description : DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY View

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

The SN54/74LS74A DUAL edge-triggered FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL CLEAR AND set inputs, AND also complementary Q AND Q outputs.
Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.

Part Name(s) : DM7474 DM7474N Fairchild
Fairchild Semiconductor
Description : DUAL POSITIVE-EDGE-TRIGGEred D-TYPE FLIP-FLOPs WITH PRESET, CLEAR AND Complementary Outputs View

General Description
This device contains two independent POSITIVE-EDGE-TRIGGEred D-TYPE FLIP-FLOPs WITH complementary outputs. The information on the D input is accepted by the FLIP-FLOPs on the positive going edge of the clock pulse. The triggering occurs at a voltage level AND is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH WITHout affecting the outputs as long as the data setup AND hold times are not violated. A LOW logic level on the PRESET or CLEAR inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Part Name(s) : SN74LS74A SN74LS74AN SN74LS74AD ONSEMI
ON Semiconductor
Description : DUAL D−Type Positive Edge−Triggered Flip−Flop View

The SN74LS74A DUAL edge-triggered FLIP-FLOP utilizes Schottky TTL circuitry to produce high speed D-TYPE FLIP-FLOPs. Each FLIP-FLOP has indiviDUAL CLEAR AND set inputs, AND also complementary Q AND Q outputs.

Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse AND is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect.
   

Part Name(s) : 74F50728 I74F50728D I74F50728N N74F50728D N74F50728N Philips
Philips Electronics
Description : Synchronizing cascaded DUAL positive edge-triggered D-TYPE FLIP-FLOP View

DESCRIPTION
The 74F50728 is a cascaded DUAL positive edge–triggered D–type featuring indiviDUAL data, clock, set AND reset inputs; also true AND complementary outputs.

FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• See 74F5074 for synchronizing DUAL D-TYPE FLIP-FLOP
• See 74F50109 for synchronizing DUAL J–K positive edge-triggered FLIP-FLOP
• See 74F50729 for synchronizing DUAL DUAL D-TYPE FLIP-FLOP WITH edge-triggered set AND reset
• Industrial temperature range available (–40°C to +85°C)

 

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