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Part Name(s) : DV74AC112 DV74AC112N DV74AC112D AVG
AVG Semiconductors=>HITEK
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Part Name(s) : SN54LS107A SN54LS107AJ SN74LS107A SN74LS107AD SN74LS107AN Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS107A is a DUAL JK FLIP-FLOP with indiviDUAL J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 /74LS107A is the same as the SN54/74LS73A but has corner power pins.

 

Part Name(s) : MC74AC113 MC74ACT113 MC74AC113N MC74ACT113N MC74AC113D MC74ACT113D Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D FLIP-FLOP (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

Part Name(s) : SN54LS109AJ SN74LS109A SN74LS109AD SN74LS109AN Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP View

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JK FLIP-FLOPs. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J and Kpins together.


Part Name(s) : 74LS73 74LS73A SB74LS73A SN54LS73A Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY View

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
TheSN54LS/74LS73A offers indiviDUAL J, K, clear, and clock inputs.These DUALFLIP-FLOPs aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will performaccording to the truth table as long as minimum set-up times are observed.Input data is transferred to the outputs on the NEGATIVE-going edge of the clock pulse.

Part Name(s) : DV74AC109 DV74ACT109 DV74AC109D DV74ACT109D DV74AC109N DV74ACT109N AVG
AVG Semiconductors=>HITEK
Description : DUAL JK Positive EDGE-TRIGGERED FLIP-FLOP View

DUAL JK Positive EDGE-TRIGGERED FLIP-FLOP

Part Name(s) : SN54LS109A SN54LS109J SN74LS109 SN74LS109D SN74LS109N Motorola
Motorola => Freescale
Description : DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP View

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JKFLIP-FLOPs. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D FLIP-FLOP by simply connecting the J and Kpins together.

 

Part Name(s) : MC74F112D MC74F112J MC74F112N MC74F112 Motorola
Motorola => Freescale
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP View

The MC74F112 contains two independent, high-speed JK FLIP-FLOPs with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the FLIP-FLOP, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH.

Part Name(s) : 74ALS112 74ALS112A 74ALS112AD 74ALS112AN Philips
Philips Electronics
Description : DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP-FLOP View

DESCRIPTION
The 74ALS112A, DUAL NEGATIVE EDGE-TRIGGERED JK-type FLIP-FLOP features indiviDUAL J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs.

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