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Hitachi
Hitachi -> Renesas Electronics
Description : DUAL 2-LINE-to-4-LINE Decoders / Demultiplexers(with open collector outputs)

DUAL 2-LINE-to-4-LINE Decoders / Demultiplexers(with open collector outputs)

This circuit features DUAL 1-line-to-4-LINE demultiplexer with indiviDUAL strobes and common binary-address inputs. When both sections are enabled by the strobes, the common binary address inputs sequentially select and route associated input dtat to the appropriate output of each section.

Description : 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES LOW POWER SCHOTTKY

 

Renesas
Renesas Electronics
Description : DUAL 2-LINE-to-4-LINE Decoders / Demultiplexers

This circuit features DUAL 1-line-to-4-LINE demultiprexer with indiviDUAL strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The indiviDUAL strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.

 

Description : DUAL 2-LINE-to-4-LINE Decoders / Demultiplexers

The HD74LS139 comprises two indiviDUAL two-line-to-four-line decoder in a single package. The active-low enable input can be used as a data line in demultiplexing applications.

Description : DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

Description : DUAL 2-LINE to 4-LINE DECODERS/DEMULTIPLEXers

General Description
These TTL circuits feature DUAL 1-line-to-4-LINE demultiplexers with indiviDUAL strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common address inputs sequentially select and route associated input data to the appropriate output of each section. The indiviDUAL strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs. The inverter following the C1 data input permits use as a 3-to-8-line decoder, or 1-to-8-line demultiplexer, without external gating. Input clamping diodes are provided on these circuits to minimize transmission-line effects and simplify system design.

Features
■Applications:
   DUAL 2-to-4-LINE decoder
   DUAL 1-to-4-LINE demultiplexer
   3-to-8-line decoder
   1-to-8-line demultiplexer
■IndiviDUAL strobes simplify cascading for decoding or demultiplexing larger words
■Input clamping diodes simplify system design
■Choice of outputs:
   Totem-pole (DM74LS155)
   Open-collector (DM74LS156)

Renesas
Renesas Electronics
Description : DUAL 2-LINE-to-4-LINE Decoders / Demultiplexers (with open collector outputs)

This circuit features DUAL 1-line-to-4-LINE demultiprexer with indiviDUAL strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The indiviDUAL strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.

Description : 3-Line-to-8-Line Decoders / Demultiplexers

The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-LINE decoder can be implemented without external inverters and a 32-LINE decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Description : 3-Line-to-8-Line Decoders / Demultiplexers

The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-LINE decoder can be implemented without external inverters and a 32-LINE decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Renesas
Renesas Electronics
Description : DUAL 2-to-4-LINE DECODERS/DEMULTIPLEXers

Description
This circuit features DUAL 1-line-to-4-LINE demultiplexer with indiviDUAL strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The indiviDUAL strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.

Features
• High Speed Operation: tpd (A or B to Y) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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