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Part Name(s) : 54HC696 54HC697 54HC698 54HC699 74HC696 74HC697 74HC698 74HC699 M54HC696 M54HC696B1R M54HC696C1R M54HC696F1R M54HC696M1R M54HC697 M54HC697B1R M54HC697C1R M54HC697F1R M54HC697M1R M54HC698 M54HC698B1R M54HC698C1R M54HC698F1R M54HC698M1R M54HC699 M54HC699B1R ST-Microelectronics
STMicroelectronics
Description : HC697/699 U/D 4 BIT BINARY COUNTER/REGISTER (3-STATE) , HC696/698 U/D DECADE COUNTER/REGISTER (3-STA View

The HC696/697 are high speed CMOS up/down counters fabricated with silicon gate C2MOS technology.

They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The HC696/698 are BCD DECADE COUNTER, and the HC697/699 are 4-BIT BINARY COUNTER. Both devices have register.

They count on the positive edge of the counter clock input (CCK) when selected by the ”Counter Mode”. If the input U/D is held ”H”, the internal counter counts up, and held ”L”, counts down.

The internal counter’s outputs are stored in the output register at the positive edge of register clock (RCK). The counter features enable P and enable T and a ripple-carry output for easy expansion. the register/counter select input, R/C, selects the counter when low or the register when high for the three state outputs, QA, QB, Qc and QD.

Part Name(s) : M74HC692 M74HC692B1R M74HC692M1R M74HC692RM13TR M74HC692TTR STMICROELECTRONICS
STMicroelectronics
Description : DECADE COUNTER/REGISTER (3-STATE) View

DESCRIPTION
The M74HC692 is an high speed CMOS DECADE/COUNTER REGISTER (3 STATE) fabricated with silicon gate C2MOS technology.

■ HIGH SPEED: fMAX = 53 MHz (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
■ SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) for QA to QD OUTPUT |IOH| = IOL = 4mA (MIN) for RCO OUTPUT
■ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
■ WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 692

Part Name(s) : M54HC690 M54HC690F1R M54HC691 M54HC691F1R M54HC692 M54HC692F1R M54HC693 M54HC693F1R M74HC690B1R M74HC690C1R M74HC690M1R M74HC691B1R M74HC691C1R M74HC691M1R M74HC692B1R M74HC692C1R M74HC692M1R M74HC693B1R M74HC693C1R M74HC693M1R M74HC690 M74HC691 M74HC692 M74HC693 ST-Microelectronics
STMicroelectronics
Description : HC691/693 4 BIT BINARY COUNTER/REGISTER (3-STATE) HC690/692 DECADE COUNTER/REGISTER (3-STATE) View

DESCRIPTION
The HC690/691/692/693 are high speed CMOS COUNTER/REGISTER fabricated in silicon gate C2MOS technology.
They have the same high speed performance of LSTTL combined with true CMOS low power consumption.

■ HIGH SPEED fMAX = 50 MHz (TYP.) at VCC = 5 V
■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C
■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.)
■ OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS (for QA to QD) 10 LSTTL LOADS (for RCO)
■ SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 6 mA (MIN.) (for QA to QD) IOH = IOL = 4 mA (MIN.) (for RCO)
■ BALANCED PROPAGATION DELAYS tPLH = tPHL
■ WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V
■ PIN AND FUNCTION COMPATIBLE WITH LSTTL 54/74LS690/691

Part Name(s) : CD4029 CD4029BC CD4029BCJ CD4029BCN CD4029BM CD4029BMJ CD4029BMN CD4029BMW/883 National-Semiconductor
National ->Texas Instruments
Description : Presettable Binary/DECADE Up/Down Counter View

General Description
The CD4029BM/CD4029BC is a presettable up/down counter which counts in either binary or DECADE mode depending on the voltage level applied at binary/DECADE input. When binary/DECADE is at logical ``1'', the counter counts in binary, otherwise it counts in DECADE. Similarly, the counter counts up when the up/down input is at logical ``1'' and vice versa.
A logical ``1'' preset enable signal allows information at the ``jam'' inputs to preset the counter to any state asynchro nously with the clock. The counter is advanced one count at the positive-going edge of the clock if the carry in and preset enable inputs are at logical ``0''. Advancement is inhibited when either or both of these two inputs is at logical ``1''.
The carry out signal is normally at logical ``1'' state and goes to logical ``0'' state when the counter reaches its maximum count in the ``up'' mode or the minimum count in the ``down'' mode provided the carry input is at logical ``0'' state. All inputs are protected against static discharge by diode clamps to both VDDand VSS.

Features
Wide supply voltage range 3V to 15V
High noise immunity 0.45 VDD(typ.)
Low power fan out of 2
TTL compatibility driving 74L or 1 driving 74LS YParallel jam inputs
Binary or BCD DECADE up/down counting


Part Name(s) : M74HC390 M74HC390B1R M74HC390RM13TR ST-Microelectronics
STMicroelectronics
Description : Dual DECADE counter View

Description
The M74HC390 is an high speed CMOS dual DECADE counter fabricated with silicon gate C2MOS technology.
This dual DECADE counter contains two independent ripple carry counters. Each counter is composed of a divide by two and divide by five counter. The divide by two and divide by five counters can be cascaded to form dual DECADE, dual biquinary, or various combination up to a single divide by 100 counter.

Features
■ HIgh Speed: fMAX = 79MHz (Typ.) at VCC = 6V
■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C
■ High noise immunity: VNIH = VNIL = 28 % VCC (Min.)
■ Balanced propagation delays: tPLH ≅ tPHL
■ Wide operating voltage range: VCC (Opr) = 2V to 6V
■ Pin and function compatible with 74 series 390

Part Name(s) : HEF4534B HEF4534BD HEF4534BF HEF4534BN HEF4534BP HEF4534BT Philips
Philips Electronics
Description : LSI Real time 5-DECADE counter View

DESCRIPTION
The HEF4534B is a 5-DECADE ripple counter. The binary outputs of the DECADE counters are time-multiplexed by an internal scanner on four BCD outputs (O0 to O3). The selected DECADE is indicated by a logic HIGH on the appropriate digit select output (OS0: units, 1; OS1: tens,
10; OS2: hundreds, 102;OS3: thousands, 103; OS4: ten thousands, 104).
The binary outputs (O0to O3) and the select outputs (OS0 to OS4) are 3-STATE controlled via enable inputs EO andEOS respectively, allowing interface with other bus orientated devices. Cascading may be accomplished by using the carry out (TC). The counter is triggered by a LOW to HIGH transition on the DECADE clock (CPA) and is reset by a HIGH level on the master reset (MR).

 

 

Part Name(s) : 74HC590 74HC590BQ 74HC590D 74HC590N 74HC590PW NXP
NXP Semiconductors.
Description : 8-bit binary counter with output register; 3-STATE View

General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-STATE outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register.

Features
■ Counter and register have independent clock inputs
■ Counter has master reset
■ Complies with JEDEC standard no. 7A
■ Multiple package options
■ ESD protection:
   ◆ HBM JESD22-A114E exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V
   ◆ CDM JESD22-C101C exceeds 2000 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Part Name(s) : SN54LS192 SN54LS193 SN54LS193J SN74LS193DR2 ON-Semiconductor
ON Semiconductor
Description : PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER View

PRESETTABLE BCD/DECADE UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

The SN54/74LS192 is an UP/DOWN BCD DECADE (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.

• Low Power . . . 95 mW Typical Dissipation
• High Speed . . . 40 MHz Typical Count Frequency
• Synchronous Counting
• Asynchronous Master Reset and Parallel Load
• Individual Preset Inputs
• Cascading Circuitry Internally Provided
• Input Clamp Diodes Limit High Speed Termination Effects

Part Name(s) : HEF4029B HEF4029BD HEF4029BDB HEF4029BDF HEF4029BF HEF4029BN HEF4029BP HEF4029BPN HEF4029BT HEF4029BTD HEF4029BU Philips
Philips Electronics
Description : Synchronous up/down counter, binary/DECADE counter View

DESCRIPTION
The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD DECADE counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/DECADE control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel buffered outputs (O0 to O3) and an active LOW terminal count output (TC).
Information on P0 to P3 is asynchronously loaded into the counter while PL is HIGH, independent of CP.
The counter is advanced one count on the LOW to HIGH transition of CP when CE and PL are LOW. The TC signal is normally HIGH and goes LOW when the counter reaches its maximum count in the UP mode, or the minimum count in the DOWN mode provided CE is LOW.

 

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