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Part Name(s) : HD74LS293 HD74LS293P Renesas
RenesasRenesas
Description : 4-bit Binary Counter

4-bit Binary Counter

This counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and divide by-eight counter. This counter has a gated zero reset. To use the maximum count length of this counter, the B input is connected to the QAoutput. The input count pulses are applied to input A and the outputs are as described in the appropriate function table.

 

Part Name(s) : 7493 7493A NTE7493A NTE-Electronic
NTE-ElectronicNTE-Electronic
Description : TTL −4−Bit Binary Counter

The NTE7493A is a monolithic 4−bit binary counter in a 14−Lead DIP type package that contains four master−slave flip−flops and additional gating to provide a divide−by−two counter and a three−stage binary counter for which the count cycle length is divide−by−eight. The counter also contains a gated zero reset. To use the maximum count length of this device, the CKB input is connected to the QAoutput. The input count pulses are applied to CKA input and the outputs are as described in the function tables.

Part Name(s) : 7490 DM7490A DM7490AN Fairchild
FairchildFairchild
Description : Decade and Binary Counters

The DM7490A monolithic counter contains four master slave flip-flops and additional gating to provide a divide-by two counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated set to-nine inputs for use in BCD nine’s complement applications.

Part Name(s) : CD40192 CD40192B CD40192BMS CD40193 CD40193B CD40193BMS Intersil
IntersilIntersil
Description : CMOS Presettable Up/Down Counters (Dual Clock With Reset)

Description
CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each con sist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter.

 

Part Name(s) : 74HC40103 74HC40103D 74HC40103DB 74HC40103N 74HC40103PW Philips
PhilipsPhilips
Description : 8-bit synchronous binary down counter

The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the 40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC standard no. 7A.


The 74HC40103 consists of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic.

Part Name(s) : HEF4040 HEF4040B HEF4040BD HEF4040BF HEF4040BN HEF4040BP HEF4040BPB HEF4040BT HEF4040BU Philips
PhilipsPhilips
Description : 12-stage binary counter

DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Part Name(s) : 74HC4040 74HC4040D 74HC4040DB 74HC4040N 74HC4040PW 74HC4040U 74HCT4040 74HCT4040D 74HCT4040DB 74HCT4040N 74HCT4040PW 74HCT4040U Philips
PhilipsPhilips
Description : 12-stage binary ripple counter

The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11).

The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Part Name(s) : HEF4520B HEF4520BD HEF4520BF HEF4520BN HEF4520BP HEF4520BT Philips
PhilipsPhilips
Description : MSI Dual binary counter

DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH transition of the CP0input if CP1is HIGH or the HIGH to LOW transition of the CP1 input if CP0is low. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0to O3= LOW) independent of CP0,CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

 

Part Name(s) : 7217 ICM7217 ICM7217CIPL Intersil
IntersilIntersil
Description : 4-Digit LED Display, Programmable Up/Down Counter

The ICM7217 is a four digit, presettable up/down counter with an onboard presettable register continuously compared to the counter. The ICM7217 is intended for use in hard-wired applications where thumbwheel switches are used for loading data, and simple SPDT switchesare used for chip control.

Part Name(s) : 4017 74HC4017 74HC4017BQ 74HC4017D 74HC4017DB 74HC4017N 74HC4017PW 74HCT4017 74HCT4017BQ 74HCT4017D 74HCT4017N NXP
NXPNXP
Description : Johnson decade counter with 10 decoded outputs

The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output fromthe most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH onMR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.

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