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Part Name(s) : DS1602 DS1602S Dallas
Dallas Semiconductor -> Maxim Integrated
Description : Elapsed Time Counter

DESCRIPTION
The DS1602 is a real time clock/elapsed time counter designed to count seconds when VCC power is applied and continually count seconds under battery backup power with an additional counter regardless of the condition of VCC. The continuous counter can be used to derive time of day, week, month, and year by using a software algorithm. The VCC powered counter will automatically record the amount of time that VCC power is applied. This function is particularly useful in determining the operational time of equipment in which the DS1602 is used. Alternatively, this counter can also be used under software control to record real time events. Communication to and from the DS1602 takes place via a 3–wire serial port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. A low cost 32.768 kHz crystal attaches directly to the X1 and X2 pins. If battery powered-only operation is desired, the VBAT pin must be grounded and the VCC pin must be connected to the battery.

FEATURES
■ Two 32–bit counters keep track of real time
   and elapsed time
■ Counters keep track of seconds for over 125 years
■ Battery powered counter counts seconds from
   the time battery is attached until VBAT is less
   than 2.5 volts
■ VCC powered counter counts seconds while
   VCC is above 4.25 volts and retains the count
   in the absence of VCC under battery backup
   power
■ Clear function resets selected counter to 0
■ Read/Write serial port affords low pin count
■ Maximum current drain of less than 1 µA
   from VBAT pin when serial port is disabled
■ One byte protocol defines read/write, counter
   address and software clear function
■ 8–pin DIP or optional 8–pin SOIC
■ Operating temperature range of –40°C to +85°C
■ Reduced performance operation down to VCC = 2.5V

Part Name(s) : 54HC696 54HC697 54HC698 54HC699 74HC696 74HC697 74HC698 74HC699 M54HC696 M54HC696B1R M54HC696C1R M54HC696F1R M54HC696M1R M54HC697 M54HC697B1R M54HC697C1R M54HC697F1R M54HC697M1R M54HC698 M54HC698B1R M54HC698C1R M54HC698F1R M54HC698M1R M54HC699 M54HC699B1R ST-Microelectronics
STMicroelectronics
Description : HC697/699 U/D 4 BIT BINARY COUNTER/REGISTER (3-STATE) , HC696/698 U/D DECADE COUNTER/REGISTER (3-STA

The HC696/697 are high speed CMOS up/down counters fabricated with silicon gate C2MOS technology.

They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The HC696/698 are BCD DECADE COUNTER, and the HC697/699 are 4-BIT BINARY COUNTER. Both devices have register.

They count on the positive edge of the counter clock input (CCK) when selected by the ”Counter Mode”. If the input U/D is held ”H”, the internal counter counts up, and held ”L”, counts down.

The internal counter’s outputs are stored in the output register at the positive edge of register clock (RCK). The counter features enable P and enable T and a ripple-carry output for easy expansion. the register/counter select input, R/C, selects the counter when low or the register when high for the three state outputs, QA, QB, Qc and QD.

Part Name(s) : ICM7216A ICM7216ALJL ICM7216B ICM7216BLPL ICM7216D ICM7216DLPL Harris
Harris Semiconductor
Description : 8-Digit Multi-Function Frequency Counter/Timer

The ICM7216A and ICM7216B are fully integrated Timer Counters with LED display drivers. They combine a high frequency oscillator, a decade timebase counter, an 8-decade data counter and latches, a 7-segment decoder, digit multiplexers and 8 segment and 8 digit drivers which directly drive large multiplexed LED displays. The counter inputs have a maximum frequency of 10MHz in frequency and unit counter modes and 2MHz in the other modes. Both inputs are digital inputs. In many applications, amplification and level shifting will be required to obtain proper digital signals for these inputs.

Features All Versions
• Functions as a Frequency Counter (DC to 10MHz)
• Four Internal Gate Times: 0.01s, 0.1s, 1s, 10s in Frequency Counter Mode
• Directly Drives Digits and Segments of Large Multiplexed LED Displays (Common Anode and Common Cathode Versions)
• Single Nominal 5V Supply Required
• Highly Stable Oscillator, Uses 1MHz or 10MHz Crystal
• Internally Generated Decimal Points, Interdigit Blanking, Leading Zero Blanking and Overflow Indication
• Display Off Mode Turns Off Display and Puts Chip Into Low Power Mode
• Hold and Reset Inputs for Additional Flexibility

Features ICM7216A and ICM7216B
• Functions Also as a Period Counter, Unit Counter, Frequency Ratio Counter or Time Interval Counter
• 1 Cycle, 10 Cycles, 100 Cycles, 1000 Cycles in Period, Frequency Ratio and Time Interval Modes
• Measures Period From 0.5µs to 10s

Features ICM7216D
• Decimal Point and Leading Zero Banking May Be Externally Selected

 

Part Name(s) : DS1602S DS1602 MaximIC
Maxim Integrated
Description : Elapsed Time Counter

DESCRIPTION
The DS1602 is a real-time clock/elapsed time counter designed to count seconds when VCC power is applied and continually count seconds under battery backup power with an additional counter regardless of the condition of VCC. The continuous counter can be used to derive time of day, week, month, and year by using a software algorithm. The VCC powered counter will automatically record the amount of time that VCC power is applied. This function is particularly useful in determining the operational time of equipment in which the DS1602 is used. Alternatively, this counter can also be used under software control to record real-time events. Communication to and from the DS1602 takes place via a 3-wire serial port. A 1-byte protocol selects read/ write functions, counter clear functions and oscillator trim. A low cost 32.768kHz crystal attaches directly to the X1 and X2 pins. If battery powered-only operation is desired, the VBAT pin must be grounded and the VCC pin must be connected to the battery.

FEATURES
■ Two 32-bit counters keep track of real-time and elapsed time
■ Counters keep track of seconds for over 125 years
■ Battery powered counter counts seconds from
   the time battery is attached until VBAT is less than 2.5V
■ VCC powered counter counts seconds while
   VCC is above VTP and retains the count in the
   absence of VCC under battery backup power
■ Clear function resets selected counter to 0
■ Read/write serial port affords low pin count
■ Maximum current drain of less than 1 µA from VBAT pin when serial port is disabled
■ One byte protocol defines read/write, counter address and software clear function
■ 8-pin DIP or optional 8-pin SOIC
■ Operating temperature range of -40°C to +85°C
■ Reduced performance operation down to VCC = 2.5V
■ Underwriters Laboratory (UL) recognized

Part Name(s) : 74HC590 74HC590BQ 74HC590D 74HC590N 74HC590PW NXP
NXP Semiconductors.
Description : 8-bit binary counter with output register; 3-state

General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A.
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register.

Features
■ Counter and register have independent clock inputs
■ Counter has master reset
■ Complies with JEDEC standard no. 7A
■ Multiple package options
■ ESD protection:
   ◆ HBM JESD22-A114E exceeds 2000 V
   ◆ MM JESD22-A115-A exceeds 200 V
   ◆ CDM JESD22-C101C exceeds 2000 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C

Part Name(s) : S3C831B S3P831B SM6305 Samsung
Samsung
Description : 8-Bit CMOS Microcontroller

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS
Samsungs S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.

S3C831B MICROCONTROLLER
The S3C831B single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce power consumption.
The S3C831B is a microcontroller with a 64K-byte mask-programmable ROM embedded. The S3P831B is a microcontroller with a 64K-byte one-time-programmable ROM embedded. Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC CPU core:

— Large number of programable I/O ports (Total 72 pins)
— PLL frequency synthesizer
— 16-bits intermediate frequency counter
— Two synchronous SIO modules
— Two 8-bit timer/counters
— One 16-bit timer/counter
— Low voltage reset
— A/D converter with 8 selectable input pins

FEATURES
CPU
• SAM88RC CPU core

Memory
• 2576-byte internal register file (including LCD display RAM)
• 64K-byte internal program memory area

Instruction Set
• 78 instructions
• Idle and Stop instructions

72 I/O Pins
• 32 normal I/O pins
• 40 pins sharing with LCD segment signals

Interrupts
• 8 interrupt levels and 17 internal sources
• Fast interrupt processing feature

8-Bit Basic Timer
• Watchdog timer function
• 4 kinds of clock source

Timer/Counter 0
• Programmable 8-bit internal timer
• External event counter function
• PWM and capture function

Timer/Counter 1
• Programmable 8-bit interval timer
• External event counter function

Timer/Counter 2
• Programmable 16-bit interval timer
• External event counter function

Watch Timer
• Interval Time: 50ms, 0.5s, 1.0s at 4.5 MHz
• 1/1.5/3/6 kHz buzzer output selectable

Analog to Digital Converter
• 8-channel analog input
• 8-bit conversion resolution

Two 8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• Selectable baud rate or external clock source

PLL Frequency Synthesizer
• VIN level: 300mVpp (minimum)
• AMVCO range: 0.5 MHz–30 MHz (3-bit counter added)
• FMVCO range: 30 MHz–150 MHz

16-Bit Intermediate Frequency (IF) Counter
• VIN level: 300mVPP (minimum)
• AMIF range: 100 kHz–1 MHz
• FMIF range: 5 MHz–15 MHz

LCD Controller/Driver
• 40 segments and 4 common terminals
• 4/3/2 common and static selectable
• Internal or external resistor circuit for LCD bias

Low Voltage Reset (LVR)
• Low voltage check to make system reset
• VLVR: 2.4V, 3.7 V selectable

Two Power-Down Modes
• Idle mode: only CPU clock stops
• Stop mode: system clock and CPU clock stop

Oscillation Source
• Crystal or ceramic for system clock (fx)

Instruction Execution Time
• 444 ns at 9.0 MHz (minimum)

Operating Temperature Range
• –25 °C to +85 °C

Operating Voltage Range
• 2.2V to 5.5V at 0.4 MHz – 4.5 MHz
• 4.0 V to 5.5 V at 0.4 MHz–9.0 MHz
• 2.5V to 3.5V, 4.5 V to 5.5 V in PLL/IFC block

Package Type
• 100-QFP-1420C, 100-TQFP-1414

 

Part Name(s) : CD74HC40103-Q1 CD74HC40103QM96Q1 HC40103QM96G4Q1 TI
Texas Instruments
Description : HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER

description/ordering information
The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage synchronous down counter with a single output, which is active when the internal count is zero. The device contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC) output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches zero, if TE is low, and remains low for one full clock period.
When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE, or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset (MR) input is low, the counter asynchronously is cleared to its maximum count of 25510, regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a counting sequence of 10016 or 25610 clock pulses long.

● Qualified for Automotive Applications
● Synchronous or Asynchronous Preset
● Cascadable in Synchronous or Ripple
   Mode
● Fanout (Over Temperature Range)
   − Standard Outputs . . . 10 LSTTL Loads
   − Bus Driver Outputs . . . 15 LSTTL Loads
● Balanced Propagation Delay and Transition
   Times
● Significant Power Reduction Compared to
   LSTTL Logic ICs
● VCC Voltage = 2 V to 6 V
● High Noise Immunity NIL or NIH = 30% of
   VCC, VCC = 5 V

Part Name(s) : IW4029B IW4029BN IW4029BD INTE-ElectronicGRAL
Integral Corp.
Description : Presettable Up/Down Counter

Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS

The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY IN or PRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND when not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low.
Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package
   temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
   1.0 V min @ 5.0 V supply
   2.0 V min @ 10.0 V supply
   2.5 V min @ 15.0 V supply

Part Name(s) : S3C830A S3P830A Samsung
Samsung
Description : 8-Bit CMOS Microcontroller

PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsungs S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:

   — Efficient register-oriented architecture
   — Selectable CPU clock sources
   — Idle and Stop power-down mode release by interrupt
   — Built-in basic timer with watchdog function
  
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels.

S3C830A MICROCONTROLLER
The S3C830A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce power consumption.
The S3C830A is a microcontroller with a 48K-byte mask-programmable ROM embedded.
The S3P830A is a microcontroller with a 48K-byte one-time-programmable ROM embedded.
Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC CPU core:
   — Large number of programable I/O ports (Total 72 pins)
   — PLL frequency synthesizer
   — 16-bits intermediate frequency counter
   — Two synchronous SIO modules
   — Two 8-bit timer/counters
   — One 16-bit timer/counter
   — Low voltage reset
   — A/D converter with 4 selectable input pins
  
OTP
The S3C830A microcontroller is also available in OTP (One Time Programmable) version, S3P830A.
The S3P830A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked ROM. The S3P830A is comparable to S3C830A, both in function and in pin configuration.

FEATURES
CPU
   • SAM88RC CPU core
Memory
   • 2064-byte internal register file (including LCD display RAM)
   • 48K-byte internal program memory area
Instruction Set
   • 78 instructions
   • Idle and Stop instructions
72 I/O Pins
   • 32 normal I/O pins
   • 40 pins sharing with LCD segment signals
Interrupts
   • 8 interrupt levels and 17 internal sources
   • Fast interrupt processing feature
8-Bit Basic Timer
   • Watchdog timer function
   • 4 kinds of clock source
Timer/Counter 0
   • Programmable 8-bit internal timer
   • External event counter function
   • PWM and capture function
Timer/Counter 1
   • Programmable 8-bit interval timer
   • External event counter function
Timer/Counter 2
   • Programmable 16-bit interval timer
   • External event counter function
Watch Timer
   • Interval Time: 50ms, 0.5s, 1.0s at 4.5 MHz
   • 1/1.5/3/6 kHz buzzer output selectable
Analog to Digital Converter
   • 4-channel analog input
   • 8-bit conversion resolution

Two 8-bit Serial I/O Interface
   • 8-bit transmit/receive mode
   • 8-bit receive mode
   • Selectable baud rate or external clock source
PLL Frequency Synthesizer
   • VIN level: 300mVpp (minimum)
   • AMVCO range: 0.5 MHz–30 MHz
   • FMVCO range: 30 MHz–150 MHz
16-Bit Intermediate Frequency (IF) Counter
   • VIN level: 300mVpp (minimum)
   • AMIF range: 100 kHz–1 MHz
   • FMIF range: 5 MHz–15 MHz
LCD Controller/Driver
   • 40 segments and 4 common terminals
   • 4/3/2 common and static selectable
   • Internal or external resistor circuit for LCD bias
Low Voltage Reset (LVR)
   • Low voltage check to make system reset
   • VLVR: 3.5 V (typical)
Two Power-Down Modes
   • Idle mode: only CPU clock stops
   • Stop mode: system clock and CPU clock stop
Oscillation Source
   • Crystal or ceramic for system clock (fx)
Instruction Execution Time
   • 890 ns at 4.5 MHz (minimum)
Operating Temperature Range
   • –25 °C to +85 °C
Operating Voltage Range
   • 3.0 V to 5.5 V at 0.4 MHz–4.5 MHz
   • 4.5 V to 5.5 V in PLL/IFC block
Package Type
   • 100-pin QFP package

Part Name(s) : IW4029BD IW4029BN IW4029B IKSEMICON
IK Semicon Co., Ltd
Description : Presettable Up/Down Counter

Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS

The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY IN and PRESET ENABLE signals are low. Advancement is inhibited when the CARRY IN or PRESET ENABLE signals are high. The CARRY OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND when not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low.
Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.

• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 μA at 18 V over full package
   temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
   1.0 V min @ 5.0 V supply
   2.0 V min @ 10.0 V supply
   2.5 V min @ 15.0 V supply

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