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Part Name(s) : XRK79892 XRK79892IQ Exar
ExarExar
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION
The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other
three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packagin
• Pin compatible with MPC9892i

Part Name(s) : XRK7988 Exar
ExarExar
Description : INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION
The XRK7988 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 8x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.

FEATURES
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32-Lead LQFP Packaging
• 19.44 to 155.52 MHz

Part Name(s) : IDT2305 IDT2305-1DC IDT2305-1DCG IDT2305-1DCGI IDT2305-1DCI IDT2305-1HDC IDT2305-1HDCI IDT2305-1PGG IDT2305-1PGGI IDT
IDTIDT
Description : 3.3V ZERO DELAY CLOCK BUFFER

The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

Part Name(s) : MC10131 MC10131FN MC10131L MC10131P Motorola
MotorolaMotorola
Description : Dual Type D Master-Slave Flip-Flop

The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state nd using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.

PD = 235 mW typ/pkg (No Load)
FTog = 160 MHz typ
tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%–80%)

Part Name(s) : HEF4520B HEF4520BD HEF4520BF HEF4520BN HEF4520BP HEF4520BT Philips
PhilipsPhilips
Description : MSI Dual binary counter

DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an active HIGH clock input (CP0) and an active LOW clock input (CP1), buffered outputs from all four bit positions (O0to O3) and an active HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH transition of the CP0input if CP1is HIGH or the HIGH to LOW transition of the CP1 input if CP0is low. Either CP0 or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O0to O3= LOW) independent of CP0,CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

 

Part Name(s) : SN54LS113A SN54LS113AJ SN54LS113J SN74LS113AD SN74LS113AN SN74LS113D SN74LS113N Motorola
MotorolaMotorola
Description : Dual JK negative edge-triggered flip-flop

The SN54 /74LS113A offers individual J, K, set, and clock inputs. These monolithicdual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputsmay be allowed to change when the clock pulse is HIGH and the bistablewill perform according to the truth table as longas minimum setup timesare observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

Part Name(s) : SN54LS73 SN54LS73AJ SN54LS73J SN74LS73 SN74LS73A SN74LS73AD SN74LS73AN SN74LS73D SN74LS73N Motorola
MotorolaMotorola
Description : DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

  TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the clock pulse is HIGH and the bistable will per formaccording to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

Part Name(s) : VSC8175 Vitesse
VitesseVitesse
Description : 9.9-10.7Gb/s 16:1 Multiplexer and Clock Generator with High-speed Clock Outpu
Part Name(s) : MC10131 MC10131FN MC10131FNR2 MC10131L MC10131P ON-Semiconductor
ON-SemiconductorON-Semiconductor
Description : Dual Type D Master-Slave Flip-Flop

The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip–flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip–flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock.

• PD = 235 mW typ/pkg (No Load)
• FTog = 160 MHz typ
• tpd = 3.0 ns typ
• tr, tf = 2.5 ns typ (20%–80%)

Part Name(s) : CDC2582 CDC2582PAH TI
TITI
Description : 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

description
The CDC2582 is a high-performance, low-skew, low-jitter clock driver.

Low Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V VCC
Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs
Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs
Application for Synchronous DRAMs
Outputs Have Internal 26-Ω Series Resistors to Dampen Transmission-Line Effects
State-of-the-Art EPIC-ΙΙBBiCMOS Design Significantly Reduces Power Dissipation
Distributed VCC and Ground Pins Reduce Switching Noise
Packaged in 52-Pin Quad Flatpack

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