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Part Name(s) : RX7000 NTE-Electronic
NTE Electronics


Part Name(s) : DECB33J102KC4B ETC


    Capacitance 1000pF ±10%
    Rated voltage 6300Vdc
    Temperature characteristics (complied standard) B(JIS)
    Capacitance change rate ±10%
    Temperature range of temperature characteristics -25 to 85℃
    Operating temperature range -25 to 85℃

Part Name(s) : PIC18F65J50_09 PIC18F66J50_09 PIC18F66J55_09 PIC18F67J50_09 PIC18F85J50_09 PIC18F86J50_09 PIC18F86J55_09 PIC18F87J50_09 Microchip
Microchip Technology
Description : PIC18F87J50 Family Silicon Errata and DATA SHEET Clarification View

The PIC18F87J50 family devices that you have received conform functionally to the current Device DATA SHEET (DS39775B), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
The errata described in this document will be addressed in future revisions of the PIC18F87J50 family silicon.
DATA SHEET clarifications and corrections start on page 5, following the discussion of silicon issues.
The silicon revision level can be identified using the current version of MPLAB® IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (DATA-cke-saved-href="//">

For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3:
1. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box.
3. Select the MPLAB hardware tool (Debugger>Select Tool).
4. Perform a “Connect” operation to the device (Debugger>Connect). Depending on the devel opment tool used, the part number and Device Revision ID value appear in the Output window.

Part Name(s) : PIC12C508A_00 PIC12C509A_00 PIC12LCR509A_00 PIC12LCE518_00 PIC12LCE519_00 Microchip
Microchip Technology
Description : Errata SHEET for PIC12C508A/509A (Rev. A Silicon) View

The PIC12C5XX-parts conform functionally to the PIC12C5XX DATA SHEET (DS40139E), except for the anomalies described below:

Clarifications/Corrections to the DATA SHEET:
In the Device DATA SHEET (DS40139E), the following clarifications and corrections should be noted.
Section 13: Corrections for the DC Characteristics, Section 13.2, Section 13.3 and Section 13.4 are shown.
Corrections for the GPIO pull-up resistor ranges are shown in Table 13-1.
For the section titled “Reset”, additional information is provided on OSC1/CLKIN and OSC2/CLKOUT pin states during a MCLR.

Description : Document that summarizes the performance and other technical characteristics of a semiconductor View

Electronics component

* Manufacturer's name
* Product number and name
* List of available package formats (with images) and ordering codes
* Notable device properties
* Short functional description
* Pin connection diagram
* Absolute minimum and maximum ratings (supply voltage, power consumption, input currents, temperatures for storage, operating, soldering, etc.)
* Recommended operating conditions (as absolute minimum and maximum ratings)
* DC specifications (various temperatures, supply voltages, input currents, etc.)
* AC specifications (various temperatures, supply voltages, frequencies, etc.)
* Input/output wave shape diagram
* timing diagram
* Physical details showing minimum/typical/maximum dimensions, contact locations and sizes
* Test circuit
* Ordering codes for differing packages and performance criteria
* Liability disclaimer regarding device use in certain environments such as nuclear power plants and life support systems
* Application recommendations, such as required filter CAPACITORs, circuit board layout, etc.
Errata, often published prior to subsequent correction and relevant DATASHEET revision


Description : Selectable High Frequency LP/BP Filter Preliminary DATA SHEET View

The selectable high frequency lowpass/bandpass filter IC Is a CMOS chip that can be
configured for either a lowpass or a band pass filter. The lowpass response can be a 6
pole Butterworth, Elliptic or Bessel filter. The band pass response can be a six pole full, third or sixth octave bandpass filter. The device uses switched-CAPACITOR filters and no externa
components (except for decoupling CAPACITORs are required, Only an external clock is needed.

Part Name(s) : PSR55-7 Power-One
Power-One Inc.
Description : PSA, PSR Series DATA SHEET 1 to 6 A Switching Regulator View

Input voltage up to 144 VDC
Single output of 3.3 to 48 VDC
No input-to-output isolation

• RoHS lead solder exemption compliant
• Efficiency up to 95%
• Low input-output differential voltage
• No derating over temperature
• Board or chassis mountable

Part Name(s) : PM8611 PM8611-BIAP PMC-Sierra
Description : SBSLITE? Telecom Standard Product DATA SHEET Preliminary View

• The PM8611 SBI336 Bus Serializer (SBSLITE™) is a:
   ° Scalable Bandwidth Interconnect (SBI™) converter and Time Division Multiplexer (TDM) SBI switch.
   ° Byte-wide 77.76 MHz SBI336 bus to 777.6 MHz serial SBI336S converter.
   ° DS0, NxDS0, T1, E1, TVT1.5, TVT2, DS3 and E3 granular SBI336 to serial SBI336S switch. Supports subrate link switching with the restriction that subrate links must be symmetric in both the transmit and receive directions.
   ° Byte-wide 77.76 MHz TelecomBus to serial 777.6 MHz TelecomBus converter. This requires the TelecomBus J1 byte to be in a fixed location corresponding to a value of 0 or 522 which is immediately following the C1 octets:
   ° VT1.5, VT2, STS-1 77.76 MHz TelecomBus to serial TelecomBus switch.
• Can be used with the Narrowband Switch Elements, NSE-20G, to implement a DS0 granularity SBI Memory:Space:Memory switch scalable to 20 Gbit/s and NSE-8G, to implement a switch scalable to 8 Gbit/s. In TelecomBus mode, a 20 Gbit/s VT1.5/VT2 granularity Memory:Space:Memory switch can be implemented.
• Integrates two independent DS0 granularity Memory Switches. One switch is placed between the incoming 77.76 MHz byte-wide SBI336 bus and the transmit working and protect Serial SBI336S link. The transmit working and protect links transmit the same DATA. The other switch is placed between the receive working or protect Serial SBI336S link and the outgoing 77.76 MHz byte-wide SBI336 bus.
• Provides 125 µS nominal latency in DS0 mode. Channel Associated Signaling (CAS) latency through the SBSLITE in DS0 mode is two T1 multiframe (6 mS) or two E1 multiframe (4 mS).
• Provides less than 16 µS nominal latency in TelecomBus mode or SBI mode without DS0 level switching.
• Permits any receive or incoming byte from an input port to be mapped to any outgoing or transmit byte, respectively, on the associated output port through the Memory switch.
• Supports redundant working and protect serial SBI336S links in support of a redundant Memory:Space:Memory switch with the NSE.
• Encodes and decodes byte-wide SBI336 bus control signals for all SBI supported link types and clock modes for transport over the serial SBI336S interface.
• Encodes DATA from the Incoming SBI336 bus or TelecomBus stream to a working and protect 777.6 Mbit/s LVDS serial links with 8B/10B-based encoding.
• Decodes DATA from a working and protect 777.6 MHz low voltage differential serializer (LVDS) serial links with 8B/10B-based encoding to the Outgoing SBI336 bus or TelecomBus stream.
• In SBI mode, switches CAS bits with all DS0 DATA.
• Uses 8B/10B-based line coding protocol on the serial links to provide transition density guarantee and DC balance and to offer a greater control character vocabulary than the standard 8B/10B protocol.
• Provides optional pseudo-random bit sequence (PRBS) generation for each outgoing LVDS serial DATA link for off-line link verification. PRBS can be inserted with STS-1 granularity.
• Provides PRBS detection for each incoming LVDS serial link for off-line link verification. PRBS is verified with STS-1 granularity.
• Provides pins to coordinate updating of the connection map of the memory switch blocks in the local device, peer SBSLITE devices and companion NSE switch device.
• Can communicate with the NSE switch device over an in-band communications channel in the LVDS links. This channel includes mechanisms for central control and configuration.
• Derives all internal timing from a single 77.76 MHz system clock to a system frame pulse.
• Implemented in 1.8 V/3.3 V 0.18 µm CMOS and packaged in a 160 ball 15 mm x 15 mm PBGA.
• Consumes low power at 1.4 W.

• T1/E1 SONET/SDH Cross-connects
• T1/E1 SONET/SDH Add-Drop Multiplexers
• OC-48 Multiservice Access Multiplexers
• Channelized OC-12/OC-48 Any Service Any Port Switches
• Serial Backplane Board Interconnect
• Shelf to Shelf Cabled Serial Interconnect
• Voice Gateways


Part Name(s) : 8141A 8141B CF8141A CF8141B SM8141 SM8141AV SM8141BV NPC
Nippon Precision Circuits
Description : EL SHEET Driver View

The SM8141 is a transformer-less electrolumines cent (EL) SHEET lamp driver, capable of driving SHEETs up to 50cm2 in size. It employs built-in high with stand voltage output MOS transistors and requires few external components, making it ideal for compact driver units in portable equipment.

■ Dedicated EL driver
■ 50cm2 maximum EL SHEET drive capability
■ Noise-less smooth drive waveform
■ Two oscillators (EL and coil)(SM8141A)
■ Stand-by function (SM8141B)
■ High-efficiency MOS transistor driver
■ Dual supply operation possible (See TYPICAL APPLICATIONS)
■ 2.0 to 5.5V supply operation
■ 200Vp-p maximum drive voltage
■ 250Hz standard drive frequency
■ 8-pinVSOP package
■ Chip form



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